66AK2E05, 66AK2E02
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SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
For the range of memory addresses that includes EDMA3 channel controller (EDMA3CC) control registers
and EDMA3 transfer controller (TPTC) control registers, see Section Section 7.1. For memory offsets and
other details on EDMA3CC and TPTC Control Register entries, see the KeyStone Architecture Enhanced
Direct Memory Access 3 (EDMA3) User's Guide (SPRUGS5).
7.4.2 EDMA3 Channel Controller Configuration
Table 7-28 shows the configuration for each of the EDMA3 channel controllers present on the device.
Table 7-28. EDMA3 Channel Controller Configuration
DESCRIPTION EDMA3 CC0 EDMA3 CC1 EDMA3 CC2 EDMA3 CC3 EDMA3 CC4
Number of DMA channels in channel controller 64 64 64 64 64
Number of QDMA channels 8 8 8 8 8
Number of interrupt channels 64 64 64 64 64
Number of PaRAM set entries 512 512 512 512 512
Number of event queues 2 4 4 2 2
Number of transfer controllers 2 4 4 2 2
Memory protection existence Yes Yes Yes Yes Yes
Number of memory protection and shadow regions 8 8 8 8 8
7.4.3 EDMA3 Transfer Controller Configuration
Each transfer controller on the device is designed differently based on considerations like performance
requirements, system topology (like main TeraNet bus width, external memory bus width), etc. The
parameters that determine the transfer controller configurations are:
• FIFOSIZE: Determines the size in bytes for the data FIFO that is the temporary buffer for the in-flight
data. The data FIFO is where the read return data read by the TC read controller from the source
endpoint is stored and subsequently written out to the destination endpoint by the TC write controller.
• BUSWIDTH: The width of the read and write data buses in bytes, for the TC read and write controller,
respectively. This is typically equal to the bus width of the main TeraNet interface.
• Default Burst Size (DBS): The DBS is the maximum number of bytes per read/write command issued
by a transfer controller.
• DSTREGDEPTH: This determines the number of destination FIFO register sets. The number of
destination FIFO register sets for a transfer controller determines the maximum number of outstanding
transfer requests.
All four parameters listed above are fixed by the design of the device.
Table 7-29 shows the configuration of each of the EDMA3 transfer controllers present on the device.
Table 7-29. EDMA3 Transfer Controller Configuration
EDMA3 CC0/CC4 EDMA3 CC1 EDMA3 CC2 EDMA3CC3
PARAMETER TC0 TC1 TC0 TC1 TC2 TC3 TC0 TC1 TC2 TC3 TC0 TC1
FIFOSIZE 1024 1024 1024 1024 1024 1024 1024 1024 1024 1024 1024 1024
bytes bytes bytes bytes bytes bytes bytes bytes bytes bytes bytes bytes
BUSWIDTH 32 32 16 16 16 16 16 16 16 16 16 16
bytes bytes bytes bytes bytes bytes bytes bytes bytes bytes bytes bytes
DSTREGDEPTH 4 4 4 4 4 4 4 4 4 4 4 4
entries entries entries entries entries entries entries entries entries entries entries entries
DBS 128 128 128 128 128 128 128 128 128 128 64 64
bytes bytes bytes bytes bytes bytes bytes bytes bytes bytes bytes bytes
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