66AK2E05, 66AK2E02
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SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
Table 7-27. CIC2 Registers (continued)
ADDRESS
OFFSET REGISTER MNEMONIC REGISTER NAME
0x68C CH_MAP_REG167 Interrupt Channel Map Register for 668 to 668+3
0x690 CH_MAP_REG168 Interrupt Channel Map Register for 672 to 672+3
0x694 CH_MAP_REG169 Interrupt Channel Map Register for 676 to 676+3
0x698 CH_MAP_REG170 Interrupt Channel Map Register for 680 to 680+3
0x69C CH_MAP_REG171 Interrupt Channel Map Register for 684 to 684+3
0x800 HINT_MAP_REG0 Host Interrupt Map Register for 0 to 0+3
0x804 HINT_MAP_REG1 Host Interrupt Map Register for 4 to 4+3
0x808 HINT_MAP_REG2 Host Interrupt Map Register for 8 to 8+3
0x80C HINT_MAP_REG3 Host Interrupt Map Register for 12 to 12+3
0x810 HINT_MAP_REG4 Host Interrupt Map Register for 16 to 16+3
0x814 HINT_MAP_REG5 Host Interrupt Map Register for 20 to 20+3
0x818 HINT_MAP_REG6 Host Interrupt Map Register for 24 to 24+3
0x81C HINT_MAP_REG7 Host Interrupt Map Register for 28 to 28+3
0x820 HINT_MAP_REG8 Host Interrupt Map Register for 32 to 32+3
0x824 HINT_MAP_REG9 Host Interrupt Map Register for 36 to 36+3
0x828 HINT_MAP_REG10 Host Interrupt Map Register for 40 to 40+3
0x82C HINT_MAP_REG11 Host Interrupt Map Register for 44 to 44+3
0x830 HINT_MAP_REG12 Host Interrupt Map Register for 48 to 48+3
0x834 HINT_MAP_REG13 Host Interrupt Map Register for 52 to 52+3
0x838 HINT_MAP_REG14 Host Interrupt Map Register for 56 to 56+3
0x83C HINT_MAP_REG15 Host Interrupt Map Register for 60 to 60+3
0x840 HINT_MAP_REG16 Host Interrupt Map Register for 63 to 63+3
0x844 HINT_MAP_REG17 Host Interrupt Map Register for 66 to 66+3
0x848 HINT_MAP_REG18 Host Interrupt Map Register for 68 to 68+3
0x84C HINT_MAP_REG19 Host Interrupt Map Register for 72 to 72+3
0x850 HINT_MAP_REG20 Host Interrupt Map Register for 76 to 76+3
0x854 HINT_MAP_REG21 Host Interrupt Map Register for 80 to 80+3
0x858 HINT_MAP_REG22 Host Interrupt Map Register for 84 to 84+3
0x85C HINT_MAP_REG23 Host Interrupt Map Register for 88 to 88+3
0x860 HINT_MAP_REG24 Host Interrupt Map Register for 92 to 92+3
0x864 HINT_MAP_REG25 Host Interrupt Map Register for 94 to 94+3
0x868 HINT_MAP_REG26 Host Interrupt Map Register for 96 to 96+3
0x86C HINT_MAP_REG27 Host Interrupt Map Register for 100 to 100+3
0x1500 ENABLE_HINT_REG0 Host Int Enable Register 0
0x1504 ENABLE_HINT_REG1 Host Int Enable Register 1
0x1508 ENABLE_HINT_REG2 Host Int Enable Register 2
0x150C ENABLE_HINT_REG3 Host Int Enable Register 3
7.4 Enhanced Direct Memory Access (EDMA3) Controller
The primary purpose of the EDMA3 is to service user-programmed data transfers between two memory-
mapped slave endpoints on the device. The EDMA3 services software-driven paging transfers (e.g., data
movement between external memory and internal memory), performs sorting or subframe extraction of
various data structures, services event driven peripherals, and offloads data transfers from the device
C66x DSP CorePac or the ARM CorePac.
There are 5 EDMA channel controllers on the device:
• EDMA3CC0 has two transfer controllers: TPTC0 and TPTC1
Copyright © 2012–2015, Texas Instruments Incorporated Memory, Interrupts, and EDMA for 66AK2E0x 129
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