66AK2E05, 66AK2E02
SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
www.ti.com
Table 7-26. CIC0 Registers (continued)
ADDRESS
OFFSET REGISTER MNEMONIC REGISTER NAME
0x298 ENA_STATUS_REG6 Enabled Status Register 6
0x29C ENA_STATUS_REG7 Enabled Status Register 7
0x2A0 ENA_STATUS_REG8 Enabled Status Register 8
0x2A4 ENA_STATUS_REG9 Enabled Status Register 9
0x2A8 ENA_STATUS_REG10 Enabled Status Register10
0x2AC ENA_STATUS_REG11 Enabled Status Register 11
0x2B0 ENA_STATUS_REG12 Enabled Status Register 12
0x2B4 ENA_STATUS_REG13 Enabled Status Register 13
0x2B8 ENA_STATUS_REG14 Enabled Status Register 14
0x2BC ENA_STATUS_REG15 Enabled Status Register 15
0x300 ENABLE_REG0 Enable Register 0
0x304 ENABLE_REG1 Enable Register 1
0x308 ENABLE_REG2 Enable Register 2
0x30C ENABLE_REG3 Enable Register 3
0x310 ENABLE_REG4 Enable Register 4
0x314 ENABLE_REG5 Enable Register 5
0x318 ENABLE_REG6 Enable Register 6
0x31C ENABLE_REG7 Enable Register 7
0x320 ENABLE_REG8 Enable Register 8
0x324 ENABLE_REG9 Enable Register 9
0x328 ENABLE_REG10 Enable Register 10
0x32C ENABLE_REG11 Enable Register 11
0x330 ENABLE_REG12 Enable Register 12
0x334 ENABLE_REG13 Enable Register 13
0x338 ENABLE_REG14 Enable Register 14
0x33C ENABLE_REG15 Enable Register 15
0x380 ENABLE_CLR_REG0 Enable Clear Register 0
0x384 ENABLE_CLR_REG1 Enable Clear Register 1
0x388 ENABLE_CLR_REG2 Enable Clear Register 2
0x38C ENABLE_CLR_REG3 Enable Clear Register 3
0x390 ENABLE_CLR_REG4 Enable Clear Register 4
0x394 ENABLE_CLR_REG5 Enable Clear Register 5
0x398 ENABLE_CLR_REG6 Enable Clear Register 6
0x39C ENABLE_CLR_REG7 Enable Clear Register 7
0x3A0 ENABLE_CLR_REG8 Enable Clear Register 8
0x3A4 ENABLE_CLR_REG9 Enable Clear Register 9
0x3A8 ENABLE_CLR_REG10 Enable Clear Register 10
0x3AC ENABLE_CLR_REG11 Enable Clear Register 11
0x3B0 ENABLE_CLR_REG12 Enable Clear Register 12
0x3B4 ENABLE_CLR_REG13 Enable Clear Register 13
0x3B8 ENABLE_CLR_REG14 Enable Clear Register 14
0x38C ENABLE_CLR_REG15 Enable Clear Register 15
0x400 CH_MAP_REG0 Interrupt Channel Map Register for 0 to 0+3
0x404 CH_MAP_REG1 Interrupt Channel Map Register for 4 to 4+3
0x408 CH_MAP_REG2 Interrupt Channel Map Register for 8 to 8+3
0x40C CH_MAP_REG3 Interrupt Channel Map Register for 12 to 12+3
0x410 CH_MAP_REG4 Interrupt Channel Map Register for 16 to 16+3
120 Memory, Interrupts, and EDMA for 66AK2E0x Copyright © 2012–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: 66AK2E05 66AK2E02