66AK2E05, 66AK2E02
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SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
Table 7-25. CIC2 Event Inputs (Secondary Events for EDMA3CC and Hyperlink) (continued)
EVENT NO. EVENT NAME DESCRIPTION
473 Reserved Reserved
474 Reserved Reserved
475 Reserved Reserved
476 Reserved Reserved
477 Reserved Reserved
478 Reserved Reserved
7.3.2 CIC Registers
This section includes the CIC memory map information and registers.
7.3.2.1 CIC0 Register Map
Table 7-26. CIC0 Registers
ADDRESS
OFFSET REGISTER MNEMONIC REGISTER NAME
0x0 REVISION_REG Revision Register
0x4 CONTROL_REG Control Register
0xC HOST_CONTROL_REG Host Control Register
0x10 GLOBAL_ENABLE_HINT_REG Global Host Int Enable Register
0x20 STATUS_SET_INDEX_REG Status Set Index Register
0x24 STATUS_CLR_INDEX_REG Status Clear Index Register
0x28 ENABLE_SET_INDEX_REG Enable Set Index Register
0x2C ENABLE_CLR_INDEX_REG Enable Clear Index Register
0x34 HINT_ENABLE_SET_INDEX_REG Host Int Enable Set Index Register
0x38 HINT_ENABLE_CLR_INDEX_REG Host Int Enable Clear Index Register
0x200 RAW_STATUS_REG0 Raw Status Register 0
0x204 RAW_STATUS_REG1 Raw Status Register 1
0x208 RAW_STATUS_REG2 Raw Status Register 2
0x20C RAW_STATUS_REG3 Raw Status Register 3
0x210 RAW_STATUS_REG4 Raw Status Register 4
0x214 RAW_STATUS_REG5 Raw Status Register 5
0x218 RAW_STATUS_REG6 Raw Status Register 6
0x21C RAW_STATUS_REG7 Raw Status Register 7
0x220 RAW_STATUS_REG8 Raw Status Register 8
0x224 RAW_STATUS_REG9 Raw Status Register 9
0x228 RAW_STATUS_REG10 Raw Status Register 10
0x22C RAW_STATUS_REG11 Raw Status Register 11
0x230 RAW_STATUS_REG12 Raw Status Register 12
0x234 RAW_STATUS_REG13 Raw Status Register 13
0x238 RAW_STATUS_REG14 Raw Status Register 14
0x23C RAW_STATUS_REG15 Raw Status Register 15
0x280 ENA_STATUS_REG0 Enabled Status Register 0
0x284 ENA_STATUS_REG1 Enabled Status Register 1
0x288 ENA_STATUS_REG2 Enabled Status Register 2
0x28C ENA_STATUS_REG3 Enabled Status Register 3
0x290 ENA_STATUS_REG4 Enabled Status Register 4
0x294 ENA_STATUS_REG5 Enabled Status Register 5
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