66AK2E05, 66AK2E02
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SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
Table 7-25. CIC2 Event Inputs (Secondary Events for EDMA3CC and Hyperlink) (continued)
EVENT NO. EVENT NAME DESCRIPTION
3 GPIO_INT11 GPIO interrupt
4 GPIO_INT12 GPIO interrupt
5 GPIO_INT13 GPIO interrupt
6 GPIO_INT14 GPIO interrupt
7 GPIO_INT15 GPIO interrupt
8 DBGTBR_DMAINT Debug trace buffer (TBR) DMA event
9 Reserved Reserved
10 Reserved Reserved
11 TETB_FULLINT0 TETB0 is full
12 TETB_HFULLINT0 TETB0 is half full
13 TETB_ACQINT0 TETB0 acquisition has been completed
14 Reserved Reserved
15 Reserved Reserved
16 Reserved Reserved
17 Reserved Reserved
18 Reserved Reserved
19 Reserved Reserved
20 Reserved Reserved
21 Reserved Reserved
22 Reserved Reserved
23 DFT_PBIST_CPU_INT Reserved
24 QMSS_INTD_1_HIGH_16 Navigator interrupt
25 QMSS_INTD_1_HIGH_17 Navigator interrupt
26 QMSS_INTD_1_HIGH_18 Navigator interrupt
27 QMSS_INTD_1_HIGH_19 Navigator interrupt
28 QMSS_INTD_1_HIGH_20 Navigator interrupt
29 QMSS_INTD_1_HIGH_21 Navigator interrupt
30 QMSS_INTD_1_HIGH_22 Navigator interrupt
31 QMSS_INTD_1_HIGH_23 Navigator interrupt
32 QMSS_INTD_1_HIGH_24 Navigator interrupt
33 QMSS_INTD_1_HIGH_25 Navigator interrupt
34 QMSS_INTD_1_HIGH_26 Navigator interrupt
35 QMSS_INTD_1_HIGH_27 Navigator interrupt
36 QMSS_INTD_1_HIGH_28 Navigator interrupt
37 QMSS_INTD_1_HIGH_29 Navigator interrupt
38 QMSS_INTD_1_HIGH_30 Navigator interrupt
39 QMSS_INTD_1_HIGH_31 Navigator interrupt
40 Reserved Reserved
41 Reserved Reserved
42 Reserved Reserved
43 Reserved Reserved
44 Reserved Reserved
45 TRACER_CORE_0_INT Tracer sliding time window interrupt for DSP0 L2
46 Reserved Reserved
47 Reserved Reserved
48 Reserved Reserved
49 TRACER_DDR_INT Tracer sliding time window interrupt for MSMC-DDR3
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