BCRTM-8
62
61
60
A7
B7
C7
TI
TI
TI
AL
AL
AL
AEN 66 A5 TI AH
BCRTSEL 11 L1 TUI --
LOCK 12
24
K2
L7
TUI
TUI
AH
AL
10 J2 AL
NAME TYPE ACTIVE DESCRIPTION
CONTROL SIGNALS
54
59
B10
A8
TO
TUI
AL
AL
52 C10 TO AL
53 A11 TO AL
TI
Read. The host uses this in conjunction with CS to read an
internal BCRTM register.
Write. The host uses this in conjunction with CS to write to an
internal BCRTM register.
BC/RT Select. This selects between either the Bus Con-
troller or Remote Terminal mode. The BC/RT Mode
Select bit in the Control Register overrides this input if
the LOCK pin is not high. This pin is internally
pulled high.
Lock. When set, this pin prevents internal changes
to both the RT address and BC/RT mode select functions.
This pin is internally pulled high.
External Override. Use this in multi-redundant applica-
tions. Upon receipt, the BCRTM aborts all current activ-
ity. EXTOVR should be connected to COMSTR output of
the adjacent BCRTM when used. This pin is internally
pulled high.
Memory Chip Select Out. This is the regenerated
MEMCSI input for external RAM during the pseudo-
dual-port RAM mode. The BCRTM also uses it to select
external memory during memory accesses.
RD
WR
CS
EXTOVR
MRST
MEMCSO
MEMCSI
RRD
RWR
Memory Chip Select In. Used in the pseudo-dual-port
RAM mode only, MEMCSI is received from the host and
is propagated through to the MEMCSO.
RAM Read. In the pseudo-dual-port RAM mode, the host
uses this signal in conjunction with MEMCSO to read
from external RAM through the BCRTM. It is also the
signal the BCRTM uses to read from memory. It is
asserted following receipt of DMAG. When the BCRTM
performs multiple reads, this signal is pulsed.
RAM Write. In the pseudo-dual-port RAM mode, the
CPU and BCRTM use this to write to external RAM. This
signal is asserted following receipt of DMAG. For multi-
ple writes, this signal is pulsed.
PIN NUMBER
LCC PGA
Chip Select. This selects the BCRTM when accessing
the BCRTM’s internal register.
Address Enable. The host CPU uses AEN to indicate to the
BCRTM that the BCRTM’s address lines can be asserted;
this is a precautionary signal provided to avoid address bus
crash. If not used, it must be tied high.
Master Reset. This resets all internal state machines,
encoders, decoders, and registers. The minimum pulse
width for a successful Master Reset is 500ns.
