BCRTM-29
7.0 BUS CONTROLLER ARCHITECTURE
The BCRTM’s bus controller architecture is based on a
Command Block structure and internal, host-
programmable registers. Each message transacted over the
MIL-STD-1553B bus has an associated Command Block,
which the CPU sets up (see figures 11 and 12). The
Command Block contains all the relevant message and RT
status information as well as programmable function bits
that allow the user to select functions and interrupts. This
memory interface system is flexible due to a doubly-linked
list data structure
Figure 10. Command Block
In a doubly-linked Command Block structure, pointers
delimit each Command Block to the previous and
successive blocks (see figure 12). The linking feature eases
multiple message processing tasks and supports message
scheduling because of its ability to loop through a series of
transfers at a predetermined cycle time. A data pointer in
the command allows efficient space allocation because data
blocks only have to be configured to the exact word count
used in the message. Data pointers also provide flexibility
in data-bank switching.
A control word with bit-programmable functions and a
Message Error bit are in each Command Block. This allows
selecting individual functions for each message and
provides message validity information. The BCRTM’s
register set provides additional global parameters and
address pointers.
A programmable auto retry function is selectable from the
control word and Control Register.
The auto retry can be activated when any of the following
occurs:
• Busy Bit set in the status word
• Message Error (indicated by the RT status response)
• Response Time-Out
• Message Error detected by the Bus Controller
One to four retries are programmable on the same or
opposite bus.
The Bus Controller also has a programmable intermessage
delay timer that facilitates message transfer scheduling (see
figures 13 and 14). This timer, programmed in the control
word, automatically delays between the start of two
successive commands.
A polling function is also provided. The Bus Controller,
when programmed, compares incoming status words to a
host-specified status word and generates an interrupt if the
comparison indicates any matching bits. An Interrupt and
Continue function facilitates the host subsystem’s
synchronization by generating an interrupt when the
specified Command Block’s message is executed.
HEAD POINTER
CONTROL WORD
COMMAND WORD 1
COMMAND WORD 2 (RT-RT ONLY)
DATA LIST POINTER
STATUS WORD 1
STATUS WORD 2 (RT-RT ONLY)
TAIL POINTER
X
X IS BETWEEN 1 & 32
LAST DATA WORD
DATA WORD #2
DATA WORD #1
DATA LIST POINTER
COMMAND BLOCK
Figure 11. Data Placement
COMMAND BLOCK #1
HP
TP
#2
HP
TP
#3
HP
TP
#4
HP
TP
Figure 12. Command Block Chaining
