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5962G8957701QZC

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型号: 5962G8957701QZC
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功能描述: BCRTM
PDF文件大小: 2024.39 Kbytes
PDF页数: 共61页
制造商: ETC1[List of Unclassifed Manufacturers]
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捡单宝5962G8957701QZC
PDF页面索引
120%
BCRTM-24
A receive descriptor and a transmit descriptor are associated
with each subaddress. The descriptors reside in memory and
are listed sequentially by subaddress. By using the index
within the descriptor, the BCRTM can buffer incoming and
outgoing messages, which reduces host CPU overhead.
This message buffering also reduces the risk of incoming
messages being overwritten by subsequent incoming
messages.
Each descriptor contains a programmable interrupt structure
for subsystem notification of user-selected message
transfers and indicates when the message buffers are full.
Illegalizing subaddresses, in normal and broadcast modes,
is accomplished by using programmable bits within the
descriptor (see the RT Functional Operation section on
this page).
Message Status information -- including word count, an
internally generated time tag, and broadcast and message
validity information -- is provided for each message. The
Message Status Words are stored in a separate Message
Status Word list according to subaddress. The list’s starting
locations are programmable within the descriptor.
Message data, received or transmitted, is also stored in lists.
The message capacity of the lists and the lists’ locations are
user selectable within the descriptor.
6.1 RT Functional Operation
The RT off-loads the host computer of all routine data
transfers involved with message transfers over the 1553B
bus by providing a wide range of user-programmable
functions. These functions make the BCRTM’s operation
flexible for a variety of applications. The following
paragraphs give each function’s operational descriptions.
6.1.1 RT Subaddress Descriptor Definition
The host sets words within the descriptor (see figure 6). The
BCRTM then reads the descriptor words when servicing a
command corresponding to the specified descriptor. All bit-
selectable functions are active high and inhibited when low.
A. Control Word. The first word in the descriptor, the Control Word, selects or disables message transfers and selects an index.
Bit
Number Description
BITs
15-11 Reserved.
BIT 10 Illegal Broadcast Subaddress. Indicates to the BCRTM not to access this subaddress using broadcast
commands. The Message Error bit in the status word is set if the illegal broadcast subaddress is addressed.
Since transmit commands do not apply to broadcast, this bit applies only to receive commands.
BIT 9 Illegal Subaddress. Set by the host CPU, it indicates to the BCRTM that a command with this subaddress is
illegal. If a command uses an illegal subaddress the Message Error bit in the 1553 status word is set. The Illegal
Command Interrupt is also asserted if enabled.
BIT 8 Interrupt Upon Valid Command Received. Indicates that the BCRTM is to assert an interrupt every time a
command addresses this descriptor. The interrupt occurs just prior to post-command descriptor updating.
BIT 7 Interrupt When Index = 0. Indicates that the BCRTM initiates an interrupt when the index is decremented
to zero.
BITs 6-0 Index. These bits are for indexed message buffering. Indexing means transacting a pre-specified number of
messages before notifying the host CPU. After each message transaction, the BCRTM decrements the index by
one until index = 0. Note that the index is decremented for messages that contain message errors.
B. Message Status List Pointer. The host sets the Message Status List Pointer, the second word within the descriptor, and the
BCRTM uses it as a starting address for the Message Status List. It is incremented by one with each Message Status Word
write. If the Control Word Index is already equal to zero, the Message Status List Pointer is not incremented and the previous
Message Status Word is overwritten.
Note: A Message Status Word is written and the pointer is incremented when the BCRTM detects a message error.
C. Data List Pointer. The Data List Pointer is the third word within the descriptor. The BCRTM stores data in RAM beginning
at the address indicated by the Data List Pointer. The Data List Pointer is updated at the end of each successful message with
the next message’s starting address with the following exceptions:
If the message is erroneous, the Data List Pointer is not updated. The next message overwrites any data
corresponding to the erroneous message.
Upon receiving a message, if the index is already equal to zero, the Data List Pointer is not incremented and
data from the previous message is overwritten.
D. Reserved. The fourth descriptor word is reserved for future use.
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