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5962G8957701QZC

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型号: 5962G8957701QZC
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功能描述: BCRTM
PDF文件大小: 2024.39 Kbytes
PDF页数: 共61页
制造商: ETC1[List of Unclassifed Manufacturers]
制造商LOGO: ETC1[List of Unclassifed Manufacturers] LOGO
制造商网址:
捡单宝5962G8957701QZC
PDF页面索引
120%
BCRTM-20
4.0 SYSTEM OVERVIEW
The BCRTM can be configured for a variety of processor
and memory environments. The host processor and the
BCRTM communicate via a flexible, programmable
interrupt structure, internal registers, and a user-definable
shared memory area. The shared memory area (up to 64K)
is completely user-programmable and communicates
BCRTM control information -- message data, and status/
error information.
Built-in memory management functions designed
specifically for MIL-STD-1553 applications aid processor
off-loading. The host needs only to establish the parameters
within memory so the BCRTM can access this information
as required. For example, in the RT mode, the BCRTM can
store data associated with individual subaddresses
anywhere within its 64K address space. The BCRTM then
can automatically buffer up to 128 incoming messages of
the same subaddress, thus preventing the previous messages
from being overwritten by subsequent messages. This
buffering also extends the intervals required by the host
processor to service the data. Selecting an appropriate
MCLK frequency to meet system memory access time
requirements controls the memory access rate. The
completion of a user-defined task or the occurrence of a
user-selected event is indicated by using the extensive set
of interrupts provided.
In the BC mode, the BCRTM can process multiple
messages, assist in scheduling message lists, and provide
host-programmable functions such as auto retry. The
BCRTM is incorporated in systems with a variety of
interrupt latencies by using the Interrupt History List feature
(see Exception Handling and Interrupt Logging, page 37).
The Interrupt History List sequentially stores the events that
caused the interrupt in memory without losing information
if a host processor does not respond immediately to
an interrupt.
In the Monitor (M) mode, the BCRTM’s powerful linked
list command block structure allows it to process a series of
monitored 1553 messages without the intervention of the
host. The BCRTM can store as much bus traffic as can be
contained in its 64K memory space. In addition, the host has
the capability of instructing the BCRTM to monitor and
store data for only selected remote terminals. The host
system is responsible for initializing an area in memory that
tells the BCRTM where to store command word information
and data for each command that the BCRTM receives on
the 1553 bus. This area of memory consists of "Bus Monitor
Command Blocks." An M Command Block is very similar
to the BC Command Block in the BCRTM. The only real
differences are the direction of information flow, and that
there is no Head Pointer in the M Command Block.
5.0 SYSTEM INTERFACE
5.1 DMA Transfers
The BCRTM initiates DMA transfers whenever it executes
command blocks (BC mode) or services commands (RT
mode). DMAR initiates the transfer and is terminated by the
inactive edge of DMACK. The Address Enable (AEN)
input enables the BCRTM to output an address onto the
Address bus.
The BCRTM requests transfer cycles by asserting the
DMAR output, and initiates them when a DMAG input is
received. A DMACK output indicates that the BCRTM has
control of the Data and Address buses. The TSCTL output
is asserted when the BCRTM is actually asserting the
Address and Data buses.
To support using multiple bus masters in a system, the
BCRTM outputs the DMAGO signal that results from the
DMAG signal passing through the chip when a BCRTM bus
request was not generated (DMAR inactive). You can use
DMAGO in daisy-chained multimaster systems.
RAM
BCRTM
CPU MEMORY
CONTROL SIGNALS
RRD
RWR
MEMCSO
RD
MEMCSI
WR
Figure 3a. Pseudo-Dual-Port RAM
Control Signals
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