BCRTM-15
#8 High-Priority Interrupt Status/Reset Register
When a High-Priority Interrupt is asserted, this register indicates the event that caused it. To clear the interrupt signal and reset
the bit, write a “1” to the appropriate bit. See the corresponding bit definitions of Register 7, High-Priority Interrupt Enable
Register.
Bit
Number Description
BITs 15-9 Reserved.
BIT 8 Data Overrun.
BIT 7 Illogical Command.
BIT 6 Dynamic Bus Control Mode Received
BIT 5 Subsystem Fail.
BIT 4 End of BIT.
BIT 3 BIT Word Fail.
BIT 2 End of Command Block.
BIT 1 Message Error.
BIT 0 Standard Interrupt. The BCRTM sets this bit when any Standard Interrupt occurs, providing bit 0 of Register 7
is enabled.(Reset STDINTL output.)
#9 Standard Interrupt Enable Register
This register enables Standard Interrupt logging for any of the following enabled events (Standard Interrupt logging can also
occur for events enabled in the BC Command Block or RT Subaddress/Mode Code Descriptor):
Bit
Number Description
BITs 15-6 Reserved.
BIT 5 (RT) Illegal Broadcast Command. When set, this bit enables an interrupt indicating that an Illegal Broadcast
Command has been received.
BIT 4 (RT) Illegal Command. When set, this bit enables an interrupt indicating that an illegal command has been
received.
BIT 3 (BC) Polling Comparison Match. This enables an interrupt indicating that a polling event has occurred. The user
must also set bit 12 in the BC Command Block Control Word for this interrupt to occur.
BIT 2 (BC) Retry Fail. This bit enables an interrupt indicating that all the programmed number of retries have failed.
BIT 1 (BC, RT,M) Message Error Event. This bit enables a standard interrupt for message errors.
BIT 0 (BC,M) Command Block Interrupt and Continue. This bit enables an interrupt indicating that a Command
Block, with the Interrupt and Continue Function enabled, has been executed.
