BCRTM-14
#4 BIT (Built-In-Test) Word Register
The BCRTM uses the contents of this register when it responds to the Transmit BIT Word Mode Code (#10011). In addition,
the BCRTM writes to the two most significant bits of the BIT Word Register in response to either an Initiate Self-Test Mode
Code (RT mode) or a write to Register 11 (BIT Start Command) to indicate a BIT failure. If the BIT Word needs to be modified,
it can be read out, modified, then rewritten to this register. Note that if the processor writes a “1” to either bit 14 or 15 of this
register, it effectively induces a BIT failure.
Bit
Number Description
BIT 15 Channel B failure.
BIT 14 Channel A failure.
BIT 13-0 BIT Word. The least significant fourteen bits of the BIT Word are user programmable.
#5 Current Command Register (Read Only)
In the RT or Monitor mode, this register contains the command currently being processed. When not processing a command,
the BCRTM stores the last command or status word transmitted on the 1553B bus in this register. This register is updated only
when bit 0 of Register 0 is set. In the BC mode, this register contains the most current command sent out on the 1553B bus.
#6 Interrupt Log List Pointer Register
Initialized by the CPU, the Interrupt Log List Pointer Register indicates the start of the Interrupt Log List. After each list entry,
the BCRTM updates this register with the address of the next entry in the list. (See page 37.)
#7 High-Priority Interrupt Enable Register (Read/Write)
Setting the bits in this register causes a High-Priority Interrupt when the enabled event occurs. To service the High-Priority
Interrupt, the user reads Register 8 to determine the cause of the interrupt, then writes to Register 8 to clear the appropriate
bits. The BCRTM also provides a Standard Priority Interrupt Scheme that does not require host intervention. If High-Priority
Interrupt service is not possible in a given application, it is advisable to use the Standard Priority features.
Bit
Number Description
BITs 15-9 Reserved.
BIT 8 Data Overrun Enable. When set, this bit enables an interrupt when DMAG was not received by the BCRTM
within the allotted time needed for a successful data transfer to memory.
BIT 7 (BC) Illogical Command Error Enable. This bit enables a High-Priority Interrupt to be asserted upon the
occurrence of an Illogical Command. Illogical commands include incorrectly formatted RT-RT Command
Blocks.
BIT 6 (RT) Dynamic Bus Control Mode Code Interrupt Enable. When set, an interrupt is asserted when the
Dynamic Bus Control Mode Code is received.
BIT 5 Subsystem Fail Enable. When set, a High-Priority Interrupt is asserted after receiving a Subsystem Fail
(SSYSF) input pin.
BIT 4 End of BIT Enable. This bit indicates the end of the internal BIT routine.
BIT 3 BIT Word Fail Enable. This bit enables an interrupt indicating that the BCRTM detected a BIT failure.
BIT 2 (BC) End of Command Block List Enable (see Command Block Control Word, page 38.) This interrupt can be
superseded by other high-priority interrupts.
BIT 1 Message Error Enable. If enabled, a High-Priority Interrupt is asserted at the occurrence of a message error. If
a High-Priority Interrupt condition occurs, as the result of an enabled message error, the device will halt
operation until the user clears the interrupt by writing a “1” to Bit 1 of the High-Priority Interrupt Status/Reset
Register (Reg. #8). If this interrupt is not cleared, the BCRTM remains in the HALTED state (appearing to be
“locked up”), even if it receives a valid message. This High-Priority Interrupt scheme is necessary in order to
maintain the BCRTM’s state of operation so that the host CPU has this information available at the time of
interrupt service.
BIT 0 Standard Interrupt Enable. Setting this bit enables the STDINTL pin, but does not cause a high-priority
interrupt. If low, only the STDINTL pin is asserted when a Standard Interrupt occurs.
