BCRTM-12
3.0 INTERNAL REGISTERS
The BCRTM’s internal registers (see table 1 on pages 18-
19) enable the CPU to control the actions of the BCRTM
while maintaining low DMA overhead by the BCRTM. All
functions are active high and ignored when low unless stated
otherwise. Functions and parameters are used in both RT
and BC modes except where indicated. Registers are
addressed by the binary equivalent of their decimal number.
For example, Register 1 is addressed as 0001B. Register
usage is defined as follows:
#0 Control Register
Bit
Number Description
BIT 15 Reserved.
BIT 14 Rt Address 31. When RT31=0, the BCRTM recognizes RT Address 31 as a Broadcast command. When
RT31=1,the BCRTM treats RT Address 31 as a normal terminal address.
BIT 13 Subaddress 31. When SA31=0, the BCRTM recognizes a command word with either subaddress 0 or 31 as being
a valid code. When SA31=1, the BCRTM only recognizes a command word with a subaddress of 0 as a valid
mode code.
BIT 12 Bus Controller Time out. When the BCRTM is a BC and BCTO=0, the BCRTM allows an RT up to 16us to
respond with a status word before it declares a bus time-out. If BCTO=1, the BCRTM allows an RT up to 32us to
respond with a status word before it declares a bus time-out. In the remote terminal mode of operation, this bit
controls to RT to RT response time-out. To support the requirements of MIL-STD-1553B, this bit is set to a
logical zero.
BIT 11 Enable External Override. For use in multi-redundant systems. This bit enables the EXTOVR pin.
BIT 10 BC/RT Select. This function selects between the Bus Controller and Remote Terminal/Monitor operation
modes. It overrides the external BCRTSEL input setting if the Change Lock-Out function is not used. A reset
operation must be performed when changing between BC and RT/M modes. For monitor operation this bit
must be "0". This bit is write-only.
BIT 9 (BC) Retry on Alternate Bus. This bit enables an automatic retry to operate on alternate buses. For example, if
on bus A, with two automatic retries programmed, the automatic retries occur on bus B.
BIT 8 (RT,M) Channel B Enable. When set, this bit enables Channel B operation.
(BC) No significance.
BIT 7 (RT,M) Channel A Enable. When set, this bit enables Channel A operation.
(BC) Channel Select A/B. When set, this bit selects Channel A.
BITs 6-5 (BC) Retry Count. These bits program the number (1-4) of retries to attempt. (00 = 1 retry, 11 = 4 retries)
BIT 4 (BC) Retry on Bus Controller Message Error. This bit enables automatic retries on an error the Bus Controller
detects (see the Bus Controller Architecture section, page 29).
BIT 3 (BC) Retry on Time-Out. This bit enables an automatic retry on a response time-out condition.
BIT 2 (BC) Retry on Message Error. This bit enables an automatic retry when the Message Error bit is set in the RT’s
status word response.
BIT 1 (BC) Retry on Busy. This bit enables automatic retry on a received Busy bit in an RT status word response.
BIT 0 Start Enable. In the BC mode, this bit starts/restarts Command Block execution. In the RT or M mode,
It enables the BCRTM to receive a valid command. RT operation does not start until a valid command is
received. When using this function:
• Restart the BCRTM after each Master Reset or programmed reset.
• This bit is not readable; verify operation by reading bit 0 of the BCRTM’s Status Register.
