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590EA148M352DGR

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型号: 590EA148M352DGR
PDF文件:
  • 590EA148M352DGR PDF文件
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功能描述: 1 ps MAX JITTER CRYSTAL OSCILLATOR
PDF文件大小: 101.36 Kbytes
PDF页数: 共12页
制造商: SILABS[Silicon Laboratories]
制造商LOGO: SILABS[Silicon Laboratories] LOGO
制造商网址: http://www.silabs.com
捡单宝590EA148M352DGR
PDF页面索引
120%
Preliminary Rev. 0.25 7/09 Copyright © 2009 by Silicon Laboratories Si590/591
Si590/591
1 ps MAX JITTER CRYSTAL OSCILLATOR (XO)
(10 MH
Z TO 525 MHZ)
Features
Applications
Description
The Si590/591 XO utilizes Silicon Laboratories’ advanced DSPLL
®
circuitry
to provide a low jitter clock at high frequencies. The Si590/591 is available
with any-rat e output f requency from 10 to 525 MHz. Unlike a traditional XO,
where a unique crystal is required for each output frequency, the Si590/591
uses one fixed crystal to provide a wide range of output frequencies. This IC
based approach allows the crystal resonator to provide exceptional
frequency stability and reliability. In addition, DSPLL clock synthesis provides
superior supply noise rejection, simplifying the task of generating low jitter
clocks in no isy environmen ts typically found in co mmunication sys tems. The
Si590/591 IC based XO is factory configurable for a wide variety of user
specifications including frequency, supply voltage, output format, and
temperature stability. Specific configurations are factory programmed at time
of shipment, thereby eliminating long lead times associated with custom
oscillators.
Functional Block Diagram
Available with any-rate output
frequencies from 10 MHz to 525 MHz
3rd generation DSPLL
®
with superior
jitter performance: 1 ps max jitter
Better frequency stability than SAW-
based oscillators
Internal fundamental mode crystal
ensures high reliability
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
–40 to +85 ºC operating
temperature range
SONET/SDH (OC-3/12/48)
Networking
SD/HD SDI/3G SDI video
Test and measurement
Storage
FPGA/ASIC clock generation
Fixed
Frequency
XO
Any-rate
10–525 MHz
DSPLL
®
Clock
Synthesis
V
DD
CLK+CLK–
GND
OE
17 k *
17 k *
*Note: Output Enable High/Low Options Available – See Ordering Information
Ordering Information:
See page 6.
Pin Assignments:
See page 5 .
(Top View)
Si5602
1
2
3
6
5
4GND
OE
V
DD
CLK+
CLK–
NC
1
2
3
6
5
4GND
NC
V
DD
CLK
NC
OE
1
2
3
6
5
4GND
NC
V
DD
CLK+
CLK–
OE
Si590 (LVDS/LVPECL/CML)
Si590 (CMOS)
Si591 (LVDS/LVP ECL/CML)
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