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3020A

3020A首页预览图
型号: 3020A
PDF文件:
  • 3020A PDF文件
  • 3020A PDF在线浏览
功能描述: XC3000 Logic Cell Array Families
PDF文件大小: 473.34 Kbytes
PDF页数: 共50页
制造商: XILINX[Xilinx, Inc]
制造商LOGO: XILINX[Xilinx, Inc] LOGO
制造商网址: http://www.xilinx.com
捡单宝3020A
PDF页面索引
120%
2-105
XC3000,
XC3000A, XC3000L,
XC3100, XC3100A
Logic Cell
Array Families
Features
Complete line of five related Field Programmable
Gate Array product families
XC3000, XC3000A, XC3000L, XC3100, XC3100A
Ideal for a wide range of custom VLSI design tasks
Replaces TTL, MSI, and other PLD logic
Integrates complete sub-systems into a single
package
Avoids the NRE, time delay, and risk of
conventional masked gate arrays
High-performance CMOS static memory technology
Guaranteed toggle rates of 70 to 325 MHz, logic
delays from 9 to 2.2 ns
System clock speeds over 80 MHz
Low quiescent and active power consumption
Flexible FPGA architecture
Compatible arrays ranging from 1,000 to 7,500
gate complexity
Extensive register, combinatorial, and I/O
capabilities
High fan-out signal distribution, low-skew clock
nets
Internal 3-state bus capabilities
TTL or CMOS input thresholds
On-chip crystal oscillator amplifier
Unlimited reprogrammability
Easy design iteration
In-system logic changes
Extensive Packaging Options
Over 20 different packages
Plastic and ceramic surface-mount and pin-grid-
array packages
Thin and Very Thin Quad Flat Pack (TQFP and
VQFP) options
Ready for volume production
Standard, off-the-shelf product availability
100% factory pre-tested devices
Excellent reliability record
Complete XACT Development System
Schematic capture, automatic place and route
Logic and timing simulation
Interactive design editor for design optimization
Timing calculator
Interfaces to popular design environments like
Viewlogic, Cadence, Mentor Graphics, and others
Description
The CMOS XC3000 Class of Logic Cell Array (LCA)
families provide a group of high-performance, high-den-
sity, digital integrated circuits. Their regular, extendable,
flexible, user-programmable array architecture is com-
posed of a configuration program store plus three types of
configurable elements: a perimeter of I/O Blocks (IOBs), a
core array of Configurable Logic Bocks (CLBs) and re-
sources for interconnection. The general structure of an
LCA device is shown in Figure 1 on the next page. The
XACT development system provides schematic capture
and auto place-and-route for design entry. Logic and
timing simulation, and in-circuit emulation are available as
design verification alternatives. The design editor is used
for interactive design optimization, and to compile the data
pattern that represents the configuration program.
The LCA user logic functions and interconnections are
determined by the configuration program data stored in
internal static memory cells. The program can be loaded in
any of several modes to accommodate various system
requirements. The program data resides externally in an
EEPROM, EPROM or ROM on the application circuit
board, or on a floppy disk or hard disk. On-chip initialization
logic provides for optional automatic loading of program
data at power-up. The companion XC17XX Serial
Configuration PROMs provide a very simple serial config-
uration program storage in a one-time programmable
package.
User I/Os Horizontal Configuration
Device CLBs Array Max Flip-Flops Longlines Data Bits
XC3020, 3020A, 3020L, 3120, 3120A 64 8 x 8 64 256 16 14,779
XC3030, 3030A, 3030L, 3130, 3130A 100 10 x 10 80 360 20 22,176
XC3042, 3042A, 3042L, 3142, 3142A 144 12 x 12 96 480 24 30,784
XC3064, 3064A, 3064L, 3164, 3164A 224 16 x 14 120 688 32 46,064
XC3090, 3090A, 3090L, 3190, 3190A 320 16 x 20 144 928 40 64,160
XC3195, 3195A 484 22 x 22 176 1,320 44 94,984
Product Description
IMPORTANT NOTICE
All new designs should use XC3000A or
XC3100A. Information on XC3000 and
XC3100 is presented here as reference
for existing designs.
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