2-125
Serial Data In
CCLK
(Output)
Serial DOUT
(Output)
1
T
DSCK
2
T
CKDS
n n + 1 n + 2
n – 3 n – 2 n – 1 n
X3223
Master Serial Mode Programming Switching Characteristics
Speed Grade Min Max Units
Description Symbol
CCLK Data In setup 1 T
DSCK
60 ns
Data In hold 2
CKDS
0ns
Notes: 1. At power-up, V
CC
must rise from 2.0 V to V
CC
min in less than 25 ms. If this is not possible, configuration can be
delayed by holding RESET Low until V
CC
has reached 4.0 V (2.5 V for the XC3000L). A very long V
CC
rise time of
>100 ms, or a non-monotonically rising V
CC
may require >6-µs High level on RESET, followed by a >6-µs Low
level on RESET and D/P after V
CC
has reached 4.0 V (2.5 V for the XC3000L).
2. Configuration can be controlled by holding RESET Low with or until after the INIT of all daisy-chain slave-mode
devices is High.
3. Master-serial-mode timing is based on slave-mode testing.
