XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families
2-124
Master Serial Mode
Figure 21. Master Serial Mode
In Master Serial mode, the CCLK output of the lead LCA
device drives a Xilinx Serial PROM that feeds the LCA DIN
input. Each rising edge of the CCLK output increments the
Serial PROM internal address counter. This puts the next
data bit on the SPROM data output, connected to the LCA
DIN pin. The lead LCA device accepts this data on the
subsequent rising CCLK edge.
The lead LCA device then presents the preamble data
(and all data that overflows the lead device) on its DOUT
pin. There is an internal delay of 1.5 CCLK periods, which
means that DOUT changes on the falling CCLK edge, and
the next LCA device in the daisy-chain accepts data on the
subsequent rising CCLK edge.
The SPROM CE input can be driven from either
LDC or
DONE . Using
LDC avoids potential contention on the DIN
pin, if this pin is configured as user-I/O, but
LDC is then
restricted to be a permanently High user output. Using
DONE also avoids contention on DIN, provided the early
DONE option is invoked.
X6092
CE
GENERAL-
PURPOSE
USER I/O
PINS
M0 M1 PWRDWN
DOUT
M2
HDC
OTHER
I/O PINS
RESET
DIN
CCLK
DATA
CLK
+5 V
•
•
•
•
•
OE/RESET
XC3000
LCA
DEVICE
D/P
SCP
CEO
CASCADED
SERIAL
MEMORY
LDC
INIT
XC17xx
RESET
SLAVE LCAs WITH IDENTICAL
CONFIGURATIONS
DURING CONFIGURATION
THE 5 kΩ M2 PULL-DOWN
RESISTOR OVERCOMES THE
INTERNAL PULL-UP,
BUT IT ALLOWS M2 TO
BE USER I/O.
(LOW RESETS THE XC17xx ADDRESS POINTER)
TO CCLK OF OPTIONAL
V
CC
V
PP
+5 V
DAISY-CHAINED LCAs WITH
DIFFERENT CONFIGURATIONS
TO DIN OF OPTIONAL
IF READBACK IS
ACTIVATED, A
5-kΩ RESISTOR IS
REQUIRED IN
SERIES WITH M1
*
*
CE
DATA
CLK
OE/RESET
DAISY-CHAINED LCAs WITH
DIFFERENT CONFIGURATIONS
TO CCLK OF OPTIONAL
SLAVE LCAs WITH IDENTICAL
CONFIGURATIONS
TO DIN OF OPTIONAL
INIT
