XT
April 1999
Intel and Pentium are registered trademarks of Intel Corporation. I
2
C is a licensed trademark of Philips Electronics, N.V. American Microsystems, Inc. reserves the right to change the detail specifica-
tions as may be required to permit improvements in the design of its products.
4.5.99
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1.0 Features
•
Generates up to eighteen low-skew, non-inverting
clocks from one clock input
•
Supports up to four SDRAM DIMMs
•
Uses either I
2
C
-bus or SMBus seri al int er f ace with
Read and Write capability for individual clock output
control
•
Output enable pin tristates all clock outputs to facili-
tate board testing
•
Clock outputs skew-matched to less than 250ps
•
Less than 5ns propagation delay
•
Output impedanc e: 17
Ω
at 0.5V
DD
•
Serial interface I/O meet I
2
C specifications; all other
I/O are LVTTL/LVCMOS-compatible
• Five differerent pin configurations available:
• FS6050: 18 clock outputs in a 48-pin SSOP
• FS6051: 10 clock outputs in a 28-pin SOIC, SSOP
• FS6053: 13 clock outputs in a 28-pin SOIC
• FS6054: 14 clock outputs in a 28-pin SOIC
Figure 1: Block Diagram (FS6050)
Serial
Interface
SDRAM_(0:1)
SCL
SDA
CLK_IN
OE
FS6050
SDRAM_(2:3)
SDRAM_(4:5)
SDRAM_(6:7)
SDRAM_(8:9)
SDRAM_(10:11)
SDRAM_(12:13)
SDRAM_(14:15)
SDRAM_16
VSS_I
2
C
VDD_I
2
C
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
SDRAM_17
VSS
VDD
18
2.0 Description
The FS6050 family of CMOS clock fanout buffer ICs are
designed for high-speed motherboard applications, such
as Intel Pentium
®
II PC100-based systems with 100MHz
SDRAM.
Up to eighteen buffered, non-inverting clock outputs are
fanned-out from one clock input. Individual clocks are
skew matched to less than 250ps at 100MHz. Multiple
power and ground supplies reduce the effects of supply
noise on devic e per f ormance.
Under I
2
C-bus control, individual clock outputs may be
turned on or off. An active-low output enable is available
to force all the clock outputs to a tristate le vel for system
testing.
Figure 2: Pin Configuration (FS6050)
1 48
2
3
4
5
6
7
8
47
46
45
44
43
42
41
(reserved)
(reserved)
VDD
SDRAM_0
SDRAM_1
VSS
VDD
SDRAM_2
VSS
SDRAM_14
SDRAM_15
(reserved)
VDD
(reserved)
9
10
11
12
13
14
15
16
SDRAM_3
VSS
CLK_IN
VDD
SDRAM_4
SDRAM_5
VSS
VDD
17
18
19
20
21
22
23
SDRAM_6
SDRAM_7
VSS
VDD
SDRAM_16
VSS
VDD_I
2
C
40
39
38
37
36
35
34
33
SDRAM_10
SDRAM_11
VDD
OE
SDRAM_13
SDRAM_12
VSS
VDD
32
31
30
29
28
27
26
VSS_I
2
C
VSS
SDRAM_17
VDD
SDRAM_9
SDRAM_8
VSS
24
SDA
25
SCL
VDD
VSS
FS6050
48-pin SSOP
Figure 3: Pin Configuration (FS6051)
1
2
3
4
5
6
7
8
VDD
SDRAM_0
SDRAM_1
VSS
VDD
SDRAM_2
VSS
SDRAM_14
SDRAM_15
VDD
9
10
11
12
13
14
15
16
SDRAM_3
VSS
CLK_IN
VDD
17
18
19
20
21
22
23
SDRAM_16
VSS
VDD_I
2
C
VDD
OE
SDRAM_13
SDRAM_12
VSS
VDD
28
27
26
VSS_I
2
C
VSS
SDRAM_17
24
SDA
25
SCL
FS6051
28-pin SOIC, SSOP
Additional pin configurations are noted on Page 2.
