SA2030
sames
1/12
n Delay compensation between switching
stages.
n Interfacing of PCM systems operating
with different clocks.
n PCM concentrators and subscriber
multiplexers.
sames
SA2030
PCM FRAME ALIGNER
M74-1885
20.01.93
n
Indication of Slip, loss of frame
synchronisation, and loss of route clock
conditions.
n ISO-CMOS technology, TTL
Compatible.
n Pin-for-Pin replacement for Siemens
PEB 2030 and SM 300
n Microprocessor Interface
APPLICATIONS
n Delay compensation and clock
alignment between 2,048MHz PCM-
30 transmission lines, and terminating
equipment.
n Control of Jitter and Wander within
Digital Networks.
GENERAL DESCRIPTION
The SA2030 is designed to interface PCM-30 routes with switching systems. The device
synchronises with the frame-format of the incoming data, and outputs this data in
accordance with the bit and frame timing of the terminating equipment. The circuit is
designed to tolerate delay, drift, wander and jitter of the incoming data and clock, and thus
simplifies the design of data- and clock-recovery hardware. The internal 1½ frames
elastic buffer provides for delay compensation and wander immunity. If the bounds of
the buffer are exceeded, the SA2030 will either repeat or drop a frame. The circuit will
accurately detect incoming Alarm-Indication-Signal (AIS) conditions, in accordance with
CCITT recommendation G.737. Loss of frame alignment is indicated on both dedicated
outputs and by outputting of AIS. The circuit includes a bidirectional alarm port for
interrogation of alarm conditions.
FEATURES
n Frame Alignment Recovery and loss
in accordance with CCITT
recommendations G.732 and G.737
n Jitter and phase-wander immunity
exceed the requirements of CCITT
recommendation G.823.
n Internal 1½ frame elastic buffer.
n Detection of incoming Alarm-
Indication-Signal (AIS), and Distant
Alarm
