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N02L1618C1AB2-70I

N02L1618C1AB2-70I首页预览图
型号: N02L1618C1AB2-70I
PDF文件:
  • N02L1618C1AB2-70I PDF文件
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功能描述: 2Mb Ultra-Low Power Asynchronous CMOS SRAM 128Kx16 bit
PDF文件大小: 261.97 Kbytes
PDF页数: 共11页
制造商: NANOAMP[NanoAmp Solutions, Inc.]
制造商LOGO: NANOAMP[NanoAmp Solutions, Inc.] LOGO
制造商网址: http://www.nanoamp.com
捡单宝N02L1618C1AB2-70I
PDF页面索引
120%
Stock No. 23265-A 3
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
NanoAmp Solutions, Inc.
N02L1618C1A
Advance Information
Functional Block Diagram
Functional Description
CE WE OE UB LB
I/O
0
- I/O
15
1
1. When UB and LB are in select mode (low), I/O
0
- I/O
15
are affected as shown. When LB only is in the select mode only I/O
0
- I/O
7
are affected as shown. When UB is in the select mode only I/O
8
- I/O
15
are affected as shown.
MODE POWER
HXXXX High Z
Standby
2
2. When the device is in standby mode, control inputs (WE, OE, UB, and LB), address inputs and data input/outputs are internally
isolated from any external influence and disabled from exerting any influence externally.
Standby
L X X H H High Z
Standby
2
Standby
LL
X
3
3. When WE is invoked, the OE input is internally disabled and has no effect on the circuit.
L
1
L
1
Data In
Write
3
Active
LHL
L
1
L
1
Data Out
Read
Active
LHH
L
1
L
1
High Z Active Active
Capacitance
1
1. These parameters are verified in device characterization and are not 100% tested
Item Symbol Test Condition Min Max Unit
Input Capacitance
C
IN
V
IN
= 0V, f = 1 MHz, T
A
= 25
o
C
8pF
I/O Capacitance
C
I/O
V
IN
= 0V, f = 1 MHz, T
A
= 25
o
C
8pF
I/O
8
- I/O
15
Control
Logic
Page
Decode
Logic
Address
Inputs
A
4
- A
16
Input/
Output
Mux
and
Buffers
I/O
0
- I/O
7
Address
Word
Decode
Logic
Address
Address
Inputs
A
0
- A
3
8K Page
x 16 word
x 16 bit
RAM Array
Word Mux
CE
WE
OE
UB
LB
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