31
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
(1) 8-bit serial I/O mode
Address 001B16 is assigned to the serial I/O1 register.
When the internal synchronous clock is selected, a serial transfer
of the 8-bit serial I/O is started by a write signal to the serial I/O1
register (address 001B16).
The serial transfer status flag (b5 of address 001A16 ) of serial I/O1
control register 2 indicates the shift register status of serial I/O1,
and is set to “1” by writing into the serial I/O1 register, which be-
comes a transfer start trigger and reset to “0” after completion of 8-
bit transfer. At the same time, a serial I/O1 interrupt request occurs.
When the external synchronous clock is selected, the contents of
the serial I/O1 register are continuously shifted while transfer clocks
are input to SCLK1. Therefore, the clock needs to be controlled ex-
ternally.
(2) Automatic transfer serial I/O mode
The serial I/O1 automatic transfer controller controls the write and
read operations of the serial I/O1 register, so the function of ad-
dress 001B16 is used as a transfer counter (1-byte units).
When performing serial transfer through the serial I/O automatic
transfer RAM (addresses 0F0016 to 0FFF16), it is necessary to set
the serial I/O1 automatic transfer data pointer (address 001816)
beforehand.
Input the low-order 8 bits of the first data store address to be seri-
ally transferred to the automatic transfer data pointer set bits.
When the internal synchronous clock is selected, the transfer inter-
val for each 1-byte data can be set by the automatic transfer inter-
val set bits (b0 to b4 of address 001C16) of serial I/O1 control regis-
ter 3 in the following cases:
1. When using no handshake signal
2. When using the SRDY1 output, SBUSY1 output, and SSTB1 output
of the handshake signal independently
3. When using a combination of SRDY1 output and SSTB1 output or a
combination of SBUSY1 output and SSTB1 output of the handshake
signal
It is possible to select one of 32 different values, namely 2 to 33
cycles of the transfer clock, as a setting value.
When using the SBUSY1 output and selecting the SBUSY1 output •
SSTB1 output function selection bit (b4 of address 001A16) of serial
I/O1 control register 2 as the signal for all transfer data, provided
that the automatic transfer interval setting is valid, a transfer inter-
val is placed before the start of transmission/reception of the first
data and after the end of transmission/reception of the last data.
For SSTB1 output, regardless of the contents of the SBUSY1 output •
SSTB1 output function selection bit (b4), the transfer interval for each
1-byte data is longer than the set value by 2 cycles.
Furthermore, when using a combination of SBUSY1 output and SSTB1
output as a signal for all transfer data, the transfer interval after the
end of transmission/reception of the last data is longer than the set
value by 2 cycles.
When the external synchronous clock is selected, automatic trans-
fer interval setting is disabled.
After completion of the above bit setup, if the internal synchronous
clock is selected, automatic serial transfer is started by writing the
value of “number of transfer bytes - 1” into the transfer counter
(address 001B16).
When the external synchronous clock is selected, write the value of
“number of transfer bytes - 1” into the transfer counter and input an
internal system clock interval of 5 cycles or more. After that, input
transfer clock to SCLK1.
As a transfer interval for each 1-byte data transfer, input an internal
system clock interval of 5 cycles or more from the clock rise time of
the last bit.
Regardless of whether the internal or external synchronous clock
is selected, the automatic transfer data pointer and the transfer
counter are decremented after each 1-byte data is received and
then written into the automatic transfer RAM. The serial transfer
status flag (b5 of address 001A16) is set to “1” by writing data into
the transfer counter. Writing data becomes a transfer start trigger,
and the serial transfer status flag is reset to “0” after the last data is
written into the automatic transfer RAM. At the same time, a serial
I/O1 interrupt request occurs.
The values written in the automatic transfer data pointer set bits
(b0 to b7 of address 001816) and the automatic transfer interval set
bits (b0 to b4 of address 001C16) are held in the latch.
When data is written into the transfer counter, the values latched in
the automatic transfer data pointer set bits (b0 to b7) and the auto-
matic transfer interval set bits (b0 to b4) are transferred to the
decrement counter.
Fig. 25 Structure of serial I/O1 automatic transfer data pointer
S
e
r
i
a
l
I
/
O
1
a
u
t
o
m
a
t
i
c
t
r
a
n
s
f
e
r
d
a
t
a
p
o
i
n
t
e
r
(
S
I
O
1
D
P
:
a
d
d
r
e
s
s
0
0
1
8
1
6
)
A
u
t
o
m
a
t
i
c
t
r
a
n
s
f
e
r
d
a
t
a
p
o
i
n
t
e
r
s
e
t
b
i
t
s
S
p
e
c
i
f
y
t
h
e
l
o
w
-
o
r
d
e
r
8
b
i
t
s
o
f
t
h
e
f
i
r
s
t
d
a
t
a
s
t
o
r
e
a
d
d
r
e
s
s
o
n
t
h
e
s
e
r
i
a
l
I
/
O
a
u
t
o
m
a
t
i
c
t
r
a
n
s
f
e
r
R
A
M
.
D
a
t
a
i
s
w
r
i
t
t
e
n
i
n
t
o
t
h
e
l
a
t
c
h
a
n
d
r
e
a
d
f
r
o
m
t
h
e
d
e
c
r
e
m
e
n
t
c
o
u
n
t
e
r
.
b
7b
0
