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FG324

FG324首页预览图
型号: FG324
PDF文件:
  • FG324 PDF文件
  • FG324 PDF在线浏览
功能描述: 7.5 ns pin-to-pin logic delays
PDF文件大小: 120.43 Kbytes
PDF页数: 共13页
制造商: XILINX[Xilinx, Inc]
制造商LOGO: XILINX[Xilinx, Inc] LOGO
制造商网址: http://www.xilinx.com
捡单宝FG324
PDF页面索引
120%
DS024 (v1.7) August 21, 2003 www.xilinx.com 1
Preliminary Product Specification 1-800-255-7778
© 2003 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
Features
Low power 3.3V 384 macrocell CPLD
7.5 ns pin-to-pin logic del ays
System frequencies up to 135 MHz
384 macrocells with 9,000 usable gates
Available in small footpri nt packages
- 144-pin TQFP (118 user I/O)
- 208-pin PQFP (172 user I/O)
- 256-ball FBGA (212 user I/O)
- 324-ball FBGA (220 user I/O)
Opti mized for 3.3V systems
- Ultra low power operation
- 5V tolerant I/O pins with 3.3V core supply
- A dva nc ed 0.35 micron five layer metal EEPROM
process
- Fast Zero Power™ (FZP) CMOS design
technology
- 3.3 V PCI electri cal specification compat ible
outputs (no inter nal clamp diode on any input or
I/O)
Advanced syste m featu re s
- In-system programm ing
- Input registers
- P redicta ble timi ng mode l
- Up to 23 clocks available per function block
- Excellent pin retention during design changes
- Full IEEE Standard 1149.1 boundary-scan (JTAG)
- Four global clo cks
- E ight product term control ter m s per function bl ock
Fast ISP programm ing tim es
Por t Enable pin for additional I/O
2.7V to 3.6V supply voltage at industrial grade voltage
range
Programmable slew rate control per output
Security bit prevents unauthorized access
Ref er to XPLA3 family data sheet (DS012
) for
architecture descri ption
Description
The XCR3384XL is a 3.3V, 384 macrocell CPLD targeted at
power sensitive designs that require leading edge program-
mable logic solutions. A total of 24 function blocks provide
9,000 usable gates. Pin-to-pin propagation delays are
7.5 ns wi th a maximum system frequency of 135 MHz.
TotalCMOS Design Technique for Fast
Zero Power
Xilinx offers a TotalCMOS CPLD, both in process technol-
ogy and design technique. Xilinx employs a cascade of
CMOS gates to implement its sum of products instead of
the traditional sense amp approach. This CMOS gate imple-
mentation allows Xilinx to offer CPLDs that are both high
perform ance and low power, breaking the paradigm that to
have low power, you must have low performance. Refer to
Figure 1 a nd Table 1 showing the I
CC
vs. Frequen cy of our
XCR3384XL TotalCMOS CPLD (data taken with 24
resetable up/down, 16-bit counters at 3.3V, 25°C).
0
XCR3384XL: 384 Macrocell CPLD
DS024 (v1.7) August 21, 2003
014
Prelim inary Prod uct Specification
R
Figure 1: XCR3384XL Typical I
CC
vs. Frequency at
V
CC
= 3.3V, 25°C
0
40
80
120
160
200
240
280
0 20 40 60 80 100 120 140
DS024_01_061802
Frequency (MHz)
Typical I
CC
(mA)
Table 1: Typical I
CC
vs. Frequency at V
CC
= 3.3V, 25°C
Frequency (MHz) 0 1 10 20 40 60 80 100 120 140
Typical I
CC
(mA) 0.02 2.2 24.4 42.4 82.6 123.0 155.6 187.8 227.5 258.1
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