EN005 (v1.2) February 21, 2006 www.xilinx.com 1
Errata Notification
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Introduction
Thank you for participating in the Xilinx Virtex™-4 Engineering Sample Program. As part of this program, we are pleased to
provide to you engineering samples of the Virtex-4 XC4VFX12 FPGA. Although Xilinx has made every effort to ensure the
highest possible quality, these devices are subject to the limitations described in the following errata.
Devices
These errata apply to the XC4VFX12 devices as shown in Ta ble 1 .
Hardware Errata Details (JTAG ID = 2)
This section provides a detailed description of each hardware issue known at the release time of this document.
FIFO16
The FIFO16 does not correctly generate the ALMOST EMPTY, EMPTY, ALMOST FULL, and FULL flags after the fol-
lowing sequence occurs:
1. Read or Write has reached the threshold value of ALMOST EMPTY OFFSET or ALMOST FULL OFFSET.
2. A single Read or Write operation is performed, followed by a simultaneous Read or Write operation, when active
Read and Write clock edges are very close together.
Unexpected or corrupt data can occur as a result of the flag failures, even if the ALMOST EMPTY or ALMOST FULL
flags are not being used.
This issue does not happen in FIFO16 applications where Read and Write never occur simultaneously. Workarounds
(downloadable macros) are available for users who are performing simultaneous Read/Writes. Not all workarounds will
achieve data sheet performance. See Xilinx answer record 22462 for more details, workaround solutions, and corre-
sponding performance information.
Processor Block
Frequency Performance
When using the APU controller interface, the maximum operating frequency of the processor block is 275 MHz, for -10
speed grade, 325MHz for -11 speed grades and 350MHz for -12 speed grade.
For other processor block errata and operational guidelines, please refer to answer record 20658.
Operational Guidelines
Design Software Requirements
The devices covered by these errata, unless otherwise specified, require the following Xilinx development software
installations.
• Speed specification v1.57 (or later) and Xilinx software ISE 7.1i Service Pack 4 (SP4) or later is required when
designing for the devices covered by this errata. Contact Xilinx technical support for SP4 help. Updates are
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Virtex-4 XC4VFX12CES Errata
EN005 (v1.2) February 21, 2006
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Errata Notification
Table 1: XC4VFX12 FPGA Devices Affected by These Errata
Devices XC4VFX12CES JTAG ID (Revision Code): 2, 0
Packages All
Speed Grades All
