DS897 April 6, 2016 www.xilinx.com 1
Product Specification
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Xilinx in the United States and other countries. All other trademarks are the property of their respective owners.
Introduction
The Zynq
®
-7000 All Programmable SoC Bus
Functional Model (BFM) supports the functional
simulation of Zynq-7000 based applications. It is
targeted to enable the functional verification of
Programmable Logic (PL) by mimicking the Processor
System (PS)-PL interfaces and OCM/DDR memories of
PS logic. This BFM is delivered as a package of
encrypted Verilog modules. BFM operation is
controlled by using a sequence of Verilog tasks
contained in a Verilog-syntax file.
Features
• Pin compatible and Verilog-based simulation
model.
• Supports all AXI interfaces.
• AXI 3.0 compliant.
• Sparse memory model (for DDR) and a RAM
model (for OCM).
• Verilog task-based API.
• Delivered in Vivado
®
Design Suite.
• Blocking and non-blocking interrupt support.
• Requires license to AXI BFM models.
Zynq-7000 All Programmable SoC
Bus Functional Model v2.0
DS897 April 6, 2016 Product Specification
LogiCORE IP Facts Table
Core Specifics
Supported Device
Family
(1)
1. For a complete listing of supported devices, see the Vivado IP
catalog.
Zynq
®
-7000
Supported User
Interfaces
Master: M_AXI_GP
Slave: S_AXI_GP, S_AXI_HP, S_AXI_ACP
Provided with Core
Documentation Product Specification
Design Files
Not Provided
Example Design Verilog
Test Bench Verilog
Constraints File Not Provided
Simulation Model Verilog
Supported S/W
Driver
N/A
Tested Design Tools
Design Entry Tools
Vivado
®
Design Suite
Simulation
(2)
2. The standard synthesis flow for Synplify is not supported.
For supported simulators, see the Xilinx
Design Tools: Release Notes Guide.
Support
Provided by Xilinx @ www.xilinx.com/support
