DS880 October 16, 2012 www.xilinx.com 1
Product Specification
© Copyright 2012 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of
Xilinx in the United States and other countries. All other trademarks are the property of their respective owners.
Introduction
The Xilinx LogiCORE™ IP Video Broadcaster core
provides a flexible block for replicating a single
inbound AXI4-Stream interface into multiple outbound
AXI4-Stream interfaces. Support for up to 16 outbound
AXI4-Stream interfaces is provided. AXI4-Stream data
widths from 8 to 64 are also supported.
Features
• AXI4-Stream data interfaces with Video protocol
support
• Configurable for up to 16 outbound video
interfaces
• Supports tdata width from 8 to 64, in 8-bit
increments
Video Broadcaster v1.00a
DS880 October 16, 2012 Product Specification
LogiCORE IP Facts Table
Core Specifics
Supported
Device Family
(1)
Zynq™-7000
(2)
, Artix™-7, Virtex
®
-7,
Kintex™-7,
Virtex-6, Spartan
®
-6
Supported User
Interfaces
AXI4-Stream
(3)
Resources N/A
Provided with Core
Design Files Verilog Source Code
Example Design Not Provided
Test Bench Not Provided
Constraints File Not Provided
Simulation Model Verilog Source Code
Supported
S/W Driver
(4)
N/A
Tested Design Flows
(5)
Design Entry ISE Design Suite Embedded Edition v14.3
Simulation
Mentor Graphics ModelSim, Xilinx
®
ISim
Synthesis Xilinx Synthesis Technology (XST)
Support
Provided by Xilinx @ www.xilinx.com/support
Notes:
1. For a complete list of supported derivative devices, see
Embedded Edition Derivative Device Support
.
2. Supported in ISE Design Suite implementations only.
3. Video protocol as defined in the Video IP: AXI Feature Adoption
section of (UG761)
AXI Reference Guide [Ref 1].
4. Standalone driver details can be found in the EDK or SDK
directory (<install_directory>/doc/usenglish/xilinx_drivers.htm).
Linux OS and driver support information is available from
//wiki.xilinx.com
.
5. For the supported versions of the tools, see the Xilinx Design
Tools: Release Notes Guide.
