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DS855

DS855首页预览图
型号: DS855
PDF文件:
  • DS855 PDF文件
  • DS855 PDF在线浏览
功能描述: Has user-selectable number of Kintex-7 FPGA GTX transceivers
PDF文件大小: 245.24 Kbytes
PDF页数: 共8页
制造商: XILINX[Xilinx, Inc]
制造商LOGO: XILINX[Xilinx, Inc] LOGO
制造商网址: http://www.xilinx.com
捡单宝DS855
供应商
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品牌
封装
批号
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备注
询价
  • 深圳市坤融电子有限公司

    16

    0755-2399097517318082080,13510287235肖瑶,树平航都大厦11FG11012384

  • DS8550
  • 奥简 
  • SOT23-5 
  • 2021+ 
  • 5680 
  • 一级代理现货库存 

  • 深圳市莱杰信科技有限公司

    7

    0755-28183929,0755-8321660618718561290,18207603663吴小姐0755-28183929深圳市福田区华强北上步工业区102栋西座619/香港新界中环工業大廈112-115號11012876

  • DS8550
  • 奥简 
  • SSOP32 
  • 22+ 
  • 92600 
  • 全新原装正品现货,价格最优惠,假一罚百 

PDF页面索引
120%
DS855 October 19, 2011 www.xilinx.com 1
Product Specification
© Copyright 2011 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, and other designated brands included herein are trademarks of Xilinx in
the United States and other countries. CPRI is a trademark of Siemens AG. All other trademarks are the property of their respective owners.
Introduction
The ChipScope™ Pro IBERT core for Kintex™-7 FPGA
GTX transceivers is customizable and designed for
evaluating and monitoring Kintex-7 FPGA GTX
transceivers. This core includes pattern generators and
checkers that are implemented in FPGA logic, and
access to ports and the dynamic reconfiguration port
attributes of the GTX transceivers. Communication
logic is also included to allow the design to be run-time
accessible through JTAG. This core can be used as a self-
contained or an open design, based on customer
configuration, and as described in this document.
Features
Provides a communication path between the
ChipScope Pro Analyzer software and the IBERT
core.
Has user-selectable number of Kintex-7 FPGA GTX
transceivers.
Each transceiver can be customized for the desired
line rate, reference clock rate, reference clock
source, and datapath width.
Requires a system clock that can be sourced from a
pin or one of the enabled GTX transceivers.
ChipScope Pro Integrated
Bit Error Ratio Test (IBERT)
for Kintex-7 FPGA GTX (v2.01.a)
DS855 October 19, 2011 Product Specification
LogiCORE IP Facts Table
Core Specifics
Supported
Device
Family
(1)
1. Including the variants of this FPGA device.
Kintex-7
Supported
User Interfaces
N/A
Resources
(2)
2. Resources listed here are for Kintex-7 devices. For more complete
device performance numbers, see Table 2.
Frequency
Configuration LUTs FFs
DSP
Slices
Block
RAMs
Max. Freq
(3)
3. Performance numbers listed are for Kintex-7 FPGAs. For more
complete performance data, see Performance and Resource
Utilization.
Config1
2401 4120
00
306.551 MHz
Config2
8359 14533
00
295.859 MHz
Config3
23516 41022
00
246.233 MHz
Provided with Core
Documentation
Product Specification
User Guide
Design Files Netlist
Example
Design
Verilog/VHDL
Test Bench Not Provided
Constraints
File
Xilinx Constraints and Synthesis Constraints
Simulation
Model
Not Provided
Tested Design Tools
Design Entry
Tools
Xilinx CORE Generator™ tool
Simulation Not Provided
Synthesis
Tools
Not Provided
Support
Provided by Xilinx @ www.xilinx.com/support
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