DS823 July 25, 2012 www.xilinx.com 1
Product Specification
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Introduction
The Xilinx SPI-4.2 (PL4) core implements and is
compliant with the OIF-SPI4-02.1 System Packet Interface
Phase 2 standard. This fully verified solution
interconnects physical-layer devices to link-layer
devices in 10 Gbps POS, ATM and Ethernet
applications. The core leverages SelectIO™ features to
achieve both smaller and faster SPI-4.2 products, which
enables higher-level functions such as switches,
bridges, and NPU interfaces.
Features
•Up to 700 MHz DDR on SPI-4.2 interface supporting 1.4
Gbps pin pair total bandwidth
• Supports Static and Dynamic Phase Alignment
utilizing ChipSync™ technology
• Bandwidth optimized Source core achieves
optimal bus throughput without additional FPGA
resources
• Flexible clocking options utilizing MMCM, global,
and regional clocking resources
• SelectIO technology supports flexible pin
assignment
• Configurable 64-bit or 128-bit AXI4-Stream FIFO
interface, both supporting full bandwidth
capabilities
• Supports unsegmented burst sizes up to 16K
• Optional continuous DPA window monitoring
• Optional advanced DPA diagnostics
• Multiple core support: more than 4 cores can be
implemented in a single device
• Sink and Source cores configured through Xilinx
CORE Generator™ system for easy customization
• Supports all Kintex™-7, and Virtex
®
-7 device and
package configurations
• Supports AXI4-Lite memory mapped interface to
manage static configuration, status, and calendar
• Delivers Sink and Source cores as independent
solutions—enabling flexible implementation
• Supports 1 to 256 addressable channels with fully
configurable SPI-4.2 calendar interface
• Supports LVDS or LVTTL (7 series only) Status
FIFO path operating at 1/4 or 1/8 of the data rate
• DIP-4 and DIP-2 parity generation and verification
LogiCORE IP SPI-4.2 v12.2
DS823 J uly 25, 2012 Product Specification
LogiCORE IP F a cts
Core Specifics
Device Family
(1)
Kintex-7, Virtex-7
Supported User
Interface
AXI4-Lite and AXI4-Stream
Resources Used
(2)
Alignment Type
Perf ormance
(Mbps)/Speed
LUTs Block RAM
FPGAs
64-bit static
622-700/
-1, -2, -3
4050 3 (36k BRAM)
9 (18k BRAM)
128-bit sta tic
622-700/
-1, -2, -3
4670 3 (36k BRAM)
13 (18k BRAM)
64-bit
dynamic
622-1.1 Gbps/-1
622-1.2 Gbps/-2
622-1.25Gbps/-3
5020 3 (36k BRAM)
9 (18k BRAM)
128-bit
dynamic
622-1.1 Gbps/-1
622-1.2 Gbps/-2
622-1.25 Gbps/-3
5640 3 (36k BRAM)
13 (18k BRAM)
Provided with Core
Documentation
User Guide
Release Notes
Design Files Encrypted RTL
Example Design
VHDL and Verilog
Test Bench VHDL and Verilog
Constraints Example XDC
Simulation Model VHDL and Verilog Structural Model
Supported S/W
Driver
N/A
Design Tool Requirement s
(3)
Design Entry Vivado™ Design Suite 2012.2
Simulation
Mentor Graphics ModelSim
Synopsys VCS and VCS MX
Synthesis Vivado Synthesis
Support
Provided by Xilinx, Inc.
1. F or a comple te lis ting of su pported device s , see the release
notes for this core.
2. Numbers are for default configurations in Virtex-7 devices.
See Table 16 throughTable 18 for m ore informatio n.
3. For the supported versions of the tools, see the Xilinx Design
Tools: Release Not es Guide.
