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DS742

DS742首页预览图
型号: DS742
PDF文件:
  • DS742 PDF文件
  • DS742 PDF在线浏览
功能描述: Programable clock phase and polarity
PDF文件大小: 1196.81 Kbytes
PDF页数: 共33页
制造商: XILINX[Xilinx, Inc]
制造商LOGO: XILINX[Xilinx, Inc] LOGO
制造商网址: http://www.xilinx.com
捡单宝DS742
PDF页面索引
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DS742 January 18, 2012 www.xilinx.com 1
Product Specification
© Copyright 2010–2012 Xilinx, Inc. XILINX, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, and other designated brands included herein are trademarks of Xilinx
in the United States and other countries. ARM is a registered trademark of ARM in the EU and other countries. The AMBA trademark is a registered trademark of ARM
Limited. All other trademarks are the property of their respective owners.
Introduction
The AXI Serial Peripheral Interface (SPI) connects to the
Advanced eXtensible Interface (AXI4). This core
provides a serial interface to SPI devices such as SPI
Electrically Erasable Programmable Read-Only
Memories (EEPROMs) and SPI serial flash devices. The
SPI protocol, as described in the Motorola M68HC11
data sheet, provides a simple method for a master and a
selected slave to exchange data. This 32-bit soft
Intellectual Property (IP) core is designed to interface
with the AXI4-Lite interface.
Features
AXI4-Lite interface is based on the AXI4
specification
Connects as a 32-bit AXI4-Lite slave
Supports four signal interfaces:
Master Out Slave In (MOSI)
Master In Slave Out (MISO)
Serial Clock (SC)
•SS
•Slave select (SS) bit for each slave on the SPI bus
Full-duplex operation
Master and slave SPI modes
Programable clock phase and polarity
Continuous transfer mode for automatic scanning
of a peripheral
Back-to-back transactions
Automatic or manual slave select modes
MSB/LSB first transactions
Transfer length of 8-bits, 16-bits or 32-bits
Local loopback capability for testing
Multiple master and multiple slave environment
Optional 16 element deep (an element is a byte, a
half-word or a word) transmit and receive First In
First Out (FIFO)
LogiCORE IP AXI Serial
Peripheral Interface
(AXI SPI) (v1.02.a)
DS742 January 18, 2012 Product Specification
LogiCORE IP Facts
Core Specifics
Supported Device
Family
(1)
Artix-7
(2)
, Virtex-7
(2)
, Zynq™-7000,
Kintex-7
(2)
, Virtex-6
(3)
, Spartan-6
(4)
Supported User
Interfaces
AXI4-Lite
Configuration
Resources and Frequency
Configuration 1
LUTs FFs Freq.
Block
RAMS
See Ta bl e 2 0, Tab le 1 9, Ta ble 18,
Tabl e 1 6 and Ta bl e 17 .
0
Provided with Core
Documentation Product Specification
Design Files
VHSIC Hardware Description Language
(VHDL)
Example Design N/A
Test Bench N/A
Constraints File N/A
Supported S/W
Driver
(5)
Standalone and Linux
Tested Design Tools
(6)
Design Entry Tools Xilinx Platform Studio (XPS)
Simulation Mentor Graphics ModelSim
Synthesis Tools Xilinx Synthesis Technology (XST)
Support
Provided by Xilinx @ www.xilinx.com/support
Notes:
1. For a complete listing of supported derivative devices, see the
IDS Embedded Edition Derivative Device Support
.
2. For more information, see 7 Series FPGAs Overview DS180.
3. For more information, see the Virtex-6 Family Overview Product
Specification (DS150).
4. For more information, see Spartan-6 Family Overview Product
Specification (DS160).
5. Standalone driver details can be found in the EDK or SDK
directory (<install_directory>/doc/usenglish/xilinx_drivers.htm).
Linux OS and driver support information is available from
http://wiki.xilinx.com.
6. For a listing of the supported tool versions, see the ISE Design
Suite 13: Release Note Guide.
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