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DS670

DS670首页预览图
型号: DS670
PDF文件:
  • DS670 PDF文件
  • DS670 PDF在线浏览
功能描述: Low-power CMOS EPROM process
PDF文件大小: 661.31 Kbytes
PDF页数: 共11页
制造商: XILINX[Xilinx, Inc]
制造商LOGO: XILINX[Xilinx, Inc] LOGO
制造商网址: http://www.xilinx.com
捡单宝DS670
PDF页面索引
120%
DS670 (v1.0) December 3, 2010 www.xilinx.com
Product Specification 1
© Copyright 2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other
countries. All other trademarks are the property of their respective owners.
Features
Configuration one-time programmable (OTP) read-only
memory designed to store configuration bitstreams of
Xilinx FPGA devices
On-chip address counter, incremented by each rising
edge on the clock input
Simple interface to the FPGA requires only one user
I/O pin
Cascadable for storing longer or multiple bitstreams
Programmable reset polarity (active High or active
Low) for compatibility with different FPGA solutions
Low-power CMOS EPROM process
Available in 5V version only
Programming support by leading programmer
manufacturers.
Design support using the Xilinx Alliance and
Foundation series software packages
Description
The XC1700E QPRO™ family of configuration PROMs
provide an easy-to-use, cost-effective method for storing
Xilinx FPGA configuration bitstreams.
When the FPGA is in Master Serial mode, it generates a
configuration clock that drives the PROM. A short access
time after the rising clock edge, data appears on the PROM
DATA output pin that is connected to the FPGA D
IN
pin. The
FPGA generates the appropriate number of clock pulses to
complete the configuration. Once configured, it disables the
PROM. When the FPGA is in Slave Serial mode, the PROM
and the FPGA must both be clocked by an incoming signal.
Multiple devices can be concatenated by using the CEO
output to drive the CE
input of the following device. The
clock inputs and the DATA outputs of all PROMs in this
chain are interconnected. All devices are compatible and
can be cascaded with other members of the family.
For device programming, either the Xilinx Alliance™ or the
Foundation™ series development systems compiles the
FPGA design file into a standard HEX format which is then
transferred to most commercial PROM programmers.
11
QPRO Family of XC1700E
Configuration PROMs
DS670 (v1.0) December 3, 2010 Product Specification
X-Ref Target - Figure 1
Figure 1: Simplified Block Diagram (Does Not Show Programming Circuit)
EPROM
Cell
Matrix
Address Counter
CE
DATA
OE
Output
CLK
V
CC
V
PP
GND
DS670_01_112910
TC
RESET/OE
or
OE/RESET
CEO
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