DS647 January 18, 2012 www.xilinx.com 1
Product Specification
© Copyright 2007–2009, 2012 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, and other designated brands included herein are trademarks
of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners.
Introduction
The LogiCORE™ IP Utility Differential Signaling
Buffer core generates corresponding buffer to bring
off-chip differential signals into internal circuit or out
from internal circuits. The core is intended as
interconnect logic between off-chip differential signals
and internal circuit.
Features
• Configurable size of the signal width
• Configurable differential signaling buffer type
LogiCORE IP Utility Differential
Signaling Buffer (v1.01a)
DS647 January 18, 2012 Product Specification
LogiCORE IP Facts Table
Core Specifics
Supported
Device Family
(1)
Zynq -7000, Artix™-7, Virtex -7, Kintex™-7,
Virtex-6, Virtex-5, Spartan -6, Virtex-4, Spartan-3
Supported User
Interfaces
N/A
Resources
See Ta ble 4
Provided with Core
Documentation Product Specification
Design Files VHDL
Example Design Not Provided
Test Bench Not Provided
Constraints File UCF
Simulation
Model
VHDL
Supported S/W
Driver
N/A
Tested Design Tools
Design Entry
Tools
ISE 13.4
Simulation
(2)
ModelSim
Synthesis
Tools
(2)
XST
Support
Provided by Xilinx @ www.xilinx.com/support
1. For a complete listing of supported devices, see the release
notes for this core.
2. For a listing of the supported tool versions, see the ISE Design
Suite 13: Release Note Guide.
