DS643 February 22, 2013 www.xilinx.com 1
Product Specification
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Introduction
The LogiCORE™ IP Multi-Port Memory Controller
(MPMC) is a fully parameterizable memory controller
that supports SDRAM/DDR/DDR2/DDR3/LPDDR
memory. The MPMC provides access to memory for
one to eight ports, where each port can be chosen from
a set of Personality Interface Modules (PIMs) that
permit connectivity into PowerPC
®
405 processors and
MicroBlaze™ processors using IBM CoreConnect
®
Toolkit Processor Local Bus (PLB) v4.6 and the Xilinx
®
CacheLink (XCL) structures, as well as a Memory
Interface Block (MIB) PIM (PPC440MC) for the
PowerPC 440 processor. The MPMC supports the Soft
Direct Memory Access (SDMA) controller that provides
full-duplex, high-bandwidth, LocalLink interfaces into
memory. A Video Frame Buffer Controller (VFBC) PIM
is also available. For low-level direct access to the
memory controller core, a Native Port Interface (NPI)
PIM is available for soft memory controllers and the
Memory Controller Block (MCB) PIM is available for
the Spartan®-6 FPGA memory controller. Additionally,
the MPMC supports optional Error Correcting Code
(ECC), Performance Monitoring (PM), and Debug
registers.
Features
• Soft Direct Memory Access (SDMA) support
• Double Data Rate (DDR/DDR2/DDR3/LPDDR)
and Single Data Rate (SDR) SDRAM support
• DIMM support (registered and unbuffered)
• Error Correcting Code (ECC) Performance
Monitoring (PM), and Debug register support
• Parameterizable:
•Number of ports (1 to 8)
• Number of data bits to memory (4, 8, 16, 32, 64)
• Configuration of datapath FIFOs
• Memory Interface Generator (MIG)-based PHY
v3.6.1 support for Spartan-3, Virtex®-4, and
Virtex-5 FPGAs
• MIG-based support (v3.9) for Spartan-6 and
Virtex-6 FPGAs
LogiCORE IP
Multi-Port Memory Controller
(v6.06.a)
DS643 February 22, 2013 Product Specification
LogiCORE IP Facts Table
Core Specifics
Supported
Device Family
(1)
1. For a complete list of supported derivative devices, see Embedded
Edition Derivative Device Support.
Virtex-6
(2)
, Spartan-6, Virtex-5,
Spartan-3/3A/3E/3AN/3A DSP, Virtex-4
2. Support for this device family is Pre-Production (designs might not
be functional in hardware or might have a limited range of
operation). Consult MIG documentation for latest device support
information.
Supported User
Interfaces
XCL, LocalLink (using SDMA), PLB v4.6 with
Xilinx simplifications, NPI, MCB,
MIB/PPC440MC, and VFBC
Resources
See Performance, Timing, and Resource
Utilization, page 188
Provided with Core
Documentation
Product Specification
Reference Documents, page 215
Design Files Verilog, VHDL
Example Design Not Provided
Test Bench Not Provided
Constraints File User Constraints File (UCF)
Simulation
Model
Cadence IES (Linux only), Mentor Graphics
ModelSim
Supported S/W
Driver
Standalone
(3)
3. Standalone driver details can be found in the EDK or SDK directory
(<install_directory>/doc/usenglish/xilinx_drivers.htm).
Tested Design Flows
(4)
4. For the supported versions of the tools, see the Xilinx Design Tools:
Release Notes Guide.
Design Entry ISE Design Suite
Simulation Mentor Graphics ModelSim
Synthesis XST
Support
Provided by Xilinx @ www.xilinx.com/support
