DS635 (v2.0) September 9, 2009 www.xilinx.com
Product Specification 1
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Summary
The Xilinx® Automotive (XA) Spartan®-3E family of FPGAs
is specifically designed to meet the needs of high-volume,
cost-sensitive automotive electronics applications. The
five-member family offers densities ranging from 100,000 to
1.6 million system gates, as shown in Ta ble 1.
Introduction
XA devices are available in both extended-temperature
Q-Grade (–40°C to +125°C T
J
) and I-Grade (–40°C to
+100°C T
J
) and are qualified to the industry recognized
AEC-Q100 standard.
The XA Spartan-3E family builds on the success of the ear-
lier XA Spartan-3 family by increasing the amount of logic
per I/O, significantly reducing the cost per logic cell. New
features improve system performance and reduce the cost
of configuration. These XA Spartan-3E FPGA enhance-
ments, combined with advanced 90 nm process technology,
deliver more functionality and bandwidth per dollar than was
previously possible, setting new standards in the program-
mable logic industry.
Because of their exceptionally low cost, XA Spartan-3E
FPGAs are ideally suited to a wide range of automotive
applications, including infotainment, driver information, and
driver assistance modules.
The XA Spartan-3E family is a superior alternative to mask
programmed ASICs and ASSPs. FPGAs avoid the high ini-
tial mask set costs and lengthy development cycles, while
also permitting design upgrades in the field with no hard-
ware replacement necessary because of its inherent pro-
grammability, an impossibility with conventional ASICs and
ASSPs with their inflexible hardware architecture.
Features
• Very low-cost, high-performance logic solution for
high-volume automotive applications
• Proven advanced 90-nanometer process technology
• Multi-voltage, multi-standard SelectIO™ interface pins
- Up to 376 I/O pins or 156 differential signal pairs
- LVCMOS, LVTTL, HSTL, and SSTL single-ended
signal standards
- 3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling
- 622+ Mb/s data transfer rate per I/O
- True LVDS, RSDS, mini-LVDS, differential
HSTL/SSTL differential I/O
- Enhanced Double Data Rate (DDR) support
- DDR SDRAM support up to 266 Mb/s
• Abundant, flexible logic resources
- Densities up to 33,192 logic cells, including
optional shift register or distributed RAM support
- Efficient wide multiplexers, wide logic
- Fast look-ahead carry logic
- Enhanced 18 x 18 multipliers with optional pipeline
- IEEE 1149.1/1532 JTAG programming/debug port
• Hierarchical SelectRAM™ memory architecture
- Up to 648 Kbits of fast block RAM
- Up to 231 Kbits of efficient distributed RAM
• Up to eight Digital Clock Managers (DCMs)
- Clock skew elimination (delay locked loop)
- Frequency synthesis, multiplication, division
- High-resolution phase shifting
- Wide frequency range (5 MHz to over 300 MHz)
• Eight global clocks plus eight additional clocks per
each half of device, plus abundant low-skew routing
• Configuration interface to industry-standard PROMs
- Low-cost, space-saving SPI serial Flash PROM
- x8 or x8/x16 parallel NOR Flash PROM
• Complete Xilinx ISE
® and WebPACK™ software
support
• MicroBlaze
™ and PicoBlaze™ embedded processor
cores
• Fully compliant 32-/64-bit 33 MHz PCI™ technology
support
• Low-cost QFP and BGA packaging options
- Common footprints support easy density migration
Refer to Spartan-3E FPGA Family: Complete Data Sheet
(DS312
) for a full product description, AC and DC specifica-
tions, and package pinout descriptions. Any values shown
specifically in this XA Spartan-3E Automotive FPGA Family
data sheet override those shown in DS312.
For information regarding reliability qualification, refer to
RPT081 (Xilinx Spartan-3E Family Automotive Qualification
Report) and RPT012 (Spartan-3/3E UMC-12A 90 nm Qual-
ification Report).
37
XA Spartan-3E Automotive
FPGA Family Data Sheet
DS635 (v2.0) September 9, 2009
0
Product Specification
