DS632 June 24, 2009 www.xilinx.com 1
Product Specification
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other trademarks are the property of their respective owners. The PowerPC name and logo are registered trademarks of IBM Corp., and used under license.
Introduction
In a multiprocessor environment, the processors need
to communicate data with each other. The easiest
method is to set up inter-processor communication
through a mailbox. XPS Mailbox features a
bi-directional communication channel between two
processors. The XPS Mailbox can be connected to the
processor either through PLB or FSL interface. The PLB
interface option is available for the MicroBlaze
™
processor, PowerPC
®
processor, or any other PLBv46
master. FSL option is available for direct connection to a
MicroBlaze processor or any other FSL capable IP.
Features
• PLB interface is based on PLB v4.6 specification
• FSL interface is based on FSL v2.0 specification
•Configurable depth of mailbox
• Configurable interrupt thresholds and maskable
interrupts
• Configurable synchronous or asynchronous
operation
• Configurable interface, FSL or PLBv46, on each port
• Bi-directional communication
0
XPS Mailbox (v2.00a)
DS632 June 24, 2009
00
Product Specification
LogiCORE™ Facts
Core Specifics
Supported Device
Family
Spartan
®
-3, Spartan-3E,
Spartan-6, Spartan-3A/3A
DSP/3AN, Automotive
Spartan-3/3A/3A DSP/ 3E,
Virtex
®
-4, Virtex-4Q, Virtex-4QV,
Virtex-5, Virtex-6
Version of core xps_mailbox v2.00a
Resources Used
1
Min Max
Slices ~50 ~455
LUTs ~85 ~365
FFs ~15 ~330
Block RAMs 0 0
Special Features None
Provided with Core
Documentation Product Specification
Design File Formats VHDL
Constraints File N/A
Verification N/A
Instantiation
Templa t e
N/A
Reference Designs &
application notes
N/A
Design Tool Requirements
Xilinx Implementation
Tools
ISE® 11.1 or later
Verification
N/A
Simulation
ModelSim PE/SE 6.4b or later
Synthesis
XST
Support
Provided by Xilinx, Inc.
1. Resources for Virtex
®
-4 implementation. Minimum for 16 word
deep and FSL only. Maximum for 16 deep and PLB only
