• 当前位置:
  • 首页
  • >
  • PDF资料
  • >
  • DS626 PDF文件及第1页内容在线浏览

DS626

DS626首页预览图
型号: DS626
PDF文件:
  • DS626 PDF文件
  • DS626 PDF在线浏览
功能描述: Supports single-beat and burst transactions
PDF文件大小: 1858.78 Kbytes
PDF页数: 共41页
制造商: XILINX[Xilinx, Inc]
制造商LOGO: XILINX[Xilinx, Inc] LOGO
制造商网址: http://www.xilinx.com
捡单宝DS626
PDF页面索引
120%
DS575 June 22, 2011 www.xilinx.com 1
Product Specification
© Copyright 2008-2011 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United
States and other countries. The PowerPC name and logo are registered trademarks of IBM Corp. and used under license. All other trademarks are the property of
their respective owners.
Introduction
The Xilinx LogiCORE™ Multi-channel External
Memory Controller (XPS MCH EMC) provides the
control interface for external synchronous,
asynchronous SRAM, and Flash memory devices
through the MCH or PLB interfaces. It is assumed that
the reader is familiar with the PLB and MCH protocol.
Features
The XPS MCH EMC is a soft IP core designed for Xilinx
FPGAs and contains the following features:
Connects as a 32-bit or 64-bit slave on PLB v4.6 bus
of 32, 64, or 128 bits
Parameterizable number (0 to 4) of channel
interfaces that can be configured with a Xilinx
CacheLink (XCL) protocol (see "Reference
Documents")
Can be used with PLB interface only or MCH
interface only or in combination of both PLB and
MCH interfaces
Supports multiple (up to 4) external memory
banks
Supports single-beat and burst transactions
Supports both linear and target word cache line
transaction of 1, 4, 8 and 16. See Table 4 for more
details
Supports low latency PLB Point-to-Point topology
Supports Synchronous / Asynchronous SRAMs
and Nor Flash memory devices
Supports page mode Nor flash
Supports target-word first PLB Cacheline read and
line-word first PLB Cacheline write transactions of
4, 8 and 16 words
Supports memory data widths of 64-bit, 32-bit,
16-bit, and 8-bit
Supports data width matching
Supports configurable cycle time for read and
write operations
LogiCORE IP XPS Multi-channel
External Memory Controller
(XPS MCH EMC) (3.01a)
DS575 June 22, 2011 Product Specification
LogiCORE Facts
Core Specifics
Supported Device
Family
(1)
Virtex-6, Virtex-5/5TX/5FX,
Virtex-4/4Q/4QR, Spartan-6,
Spartan-3, Spartan-3A, Spartan-3E,
Spartan-3A DSP, Automotive
Spartan-3/3E/3A/3A DSP
Supported User
Interfaces
MCH and PLB
Resources Used
See Ta ble 1 6 , Ta bl e 17 , Tabl e 18 , Tabl e 19 and Tabl e 20
Provided with Core
Documentation Product Specification
Design File Formats VHDL
Constraints File N/A
Verification N/A
Instantiation Template N/A
Reference Designs &
Application Notes
N/A
Design Tool Requirements
(2)
Xilinx Implementation
To o ls
XPS 13.2
Verification N/A
Simulation ModelSim PE/SE
Synthesis ISE 13.2
Support
Provided by Xilinx, Inc.
Notes:
1. For a complete listing of supported devices, see the release
notes for this core.
2. For a listing of the supported tool versions, see the ISE Design
Suite 13: Release Note Guide.
购买、咨询产品请填写询价信息:(3分钟左右您将得到回复)
询价型号*数量*批号封装品牌其它要求
删除
删除
删除
删除
删除
增加行数
  •  公司名:
  • *联系人:
  • *邮箱:
  • *电话:
  •  QQ:
  •  微信:

  • 关注官方微信

  • 联系我们
  • 电话:13714778017
  • 周一至周六:9:00-:18:00
  • 在线客服:

天天IC网由深圳市四方好讯科技有限公司独家运营

天天IC网 ( www.ttic.cc ) 版权所有©2014-2023 粤ICP备15059004号

因腾讯功能限制,可能无法唤起QQ临时会话,(点此复制QQ,添加好友),建议您使用TT在线询价。

继续唤起QQ 打开TT询价