DS575 June 22, 2011 www.xilinx.com 1
Product Specification
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Introduction
The Xilinx LogiCORE™ Multi-channel External
Memory Controller (XPS MCH EMC) provides the
control interface for external synchronous,
asynchronous SRAM, and Flash memory devices
through the MCH or PLB interfaces. It is assumed that
the reader is familiar with the PLB and MCH protocol.
Features
The XPS MCH EMC is a soft IP core designed for Xilinx
FPGAs and contains the following features:
• Connects as a 32-bit or 64-bit slave on PLB v4.6 bus
of 32, 64, or 128 bits
• Parameterizable number (0 to 4) of channel
interfaces that can be configured with a Xilinx
CacheLink (XCL) protocol (see "Reference
Documents")
• Can be used with PLB interface only or MCH
interface only or in combination of both PLB and
MCH interfaces
• Supports multiple (up to 4) external memory
banks
• Supports single-beat and burst transactions
• Supports both linear and target word cache line
transaction of 1, 4, 8 and 16. See Table 4 for more
details
• Supports low latency PLB Point-to-Point topology
• Supports Synchronous / Asynchronous SRAMs
and Nor Flash memory devices
• Supports page mode Nor flash
• Supports target-word first PLB Cacheline read and
line-word first PLB Cacheline write transactions of
4, 8 and 16 words
• Supports memory data widths of 64-bit, 32-bit,
16-bit, and 8-bit
• Supports data width matching
• Supports configurable cycle time for read and
write operations
LogiCORE IP XPS Multi-channel
External Memory Controller
(XPS MCH EMC) (3.01a)
DS575 June 22, 2011 Product Specification
LogiCORE Facts
Core Specifics
Supported Device
Family
(1)
Virtex-6, Virtex-5/5TX/5FX,
Virtex-4/4Q/4QR, Spartan-6,
Spartan-3, Spartan-3A, Spartan-3E,
Spartan-3A DSP, Automotive
Spartan-3/3E/3A/3A DSP
Supported User
Interfaces
MCH and PLB
Resources Used
See Ta ble 1 6 , Ta bl e 17 , Tabl e 18 , Tabl e 19 and Tabl e 20
Provided with Core
Documentation Product Specification
Design File Formats VHDL
Constraints File N/A
Verification N/A
Instantiation Template N/A
Reference Designs &
Application Notes
N/A
Design Tool Requirements
(2)
Xilinx Implementation
To o ls
XPS 13.2
Verification N/A
Simulation ModelSim PE/SE
Synthesis ISE 13.2
Support
Provided by Xilinx, Inc.
Notes:
1. For a complete listing of supported devices, see the release
notes for this core.
2. For a listing of the supported tool versions, see the ISE Design
Suite 13: Release Note Guide.