DS620 October 19, 2011 www.xilinx.com 1
Product Specification
© Copyright 2007–2011 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, and other designated brands included herein are trademarks of
Xilinx in the United States and other countries. All other trademarks are the property of their respective owners.
Introduction
The Xilinx® Platform Studio (XPS) System Monitor
(SYSMON) Analog-to-Digital Converter (ADC)
Intellectual Property (IP) core is a 32-bit slave
peripheral that connects to the PLB (Processor Local
Bus) and provides the controller interface for the
SYSMON hard macro on the Virtex®-5 and Virtex-6
family of Field Programmable Gate Arrays (FPGAs).
This document describes the specifications for the XPS
SYSMON ADC IP core. It is assumed that the user is
familiar with the SYSMON hard macro. For
information on the SYSMON hard macro, see the
System Monitor user guide mentioned in Reference
Documents section.
Features
• Connects as a 32-bit slave on PLB V4.6 buses of 32,
64, or 128 bits
• Uses the dedicated System Monitor (SYSMON)
hard macro on Virtex-5 and Virtex-6 devices
• Supports the 10-bit, 200-KSPS (Kilo-Samples Per
Second) Analog-to-Digital Converter (ADC)
• Supports on-chip monitoring of supply voltages
and temperature
• Supports 1 dedicated high bandwidth differential
analog-input pair and 16 auxiliary low bandwidth
differential analog-input pairs
• Supports automatic alarms based on user defined
limits
• Supports optional interrupt request generation
• Supports configurable cycle time for read and
write operations
LogiCORE IP XPS SYSMON ADC
(v3.00.b)
DS620 October 19, 2011 Product Specification
LogiCORE IP Facts Table
Core Specifics
Supported
Device Family
(1)
1. For a complete list of supported derivative devices, see the IDS
Embedded Edition Derivative Device Support.
Virtex-6
(2)
, Virtex-5
2. For more information on the Virtex-6 devices, see the DS150
Virtex-6 Family Overview
Supported User
Interfaces
PLB Interface
Resources
See Table 13 and Table 14.
Provided with Core
Documentation Product Specification
Design Files VHSIC Hardware Description Language (VHDL)
Example Design Not Provided
Test Bench Not Provided
Constraints File Not Provided
Simulation
Model
N/A
Tested Design Tools
(3)
3. For the supported versions of the tools, see the ISE Design Suite
13: Release Notes Guide.
Design Entry
Tools
XPS
Simulation ModelSim
Synthesis Tools Xilinx Synthesis Technology (XST)
Support
Provided by Xilinx @ www.xilinx.com/support