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DS617

DS617首页预览图
型号: DS617
PDF文件:
  • DS617 PDF文件
  • DS617 PDF在线浏览
功能描述: Platform Flash XL High-Density Configuration
PDF文件大小: 2358.91 Kbytes
PDF页数: 共88页
制造商: XILINX[Xilinx, Inc]
制造商LOGO: XILINX[Xilinx, Inc] LOGO
制造商网址: http://www.xilinx.com
捡单宝DS617
PDF页面索引
120%
DS617 (v3.0.1) January 07, 2010 www.xilinx.com
Product Specification 1
© 2007–2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other
countries. PCI, PCIe and PCI Express are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
Features
In-System Programmable Flash Memory Optimized for
Virtex®-5 or Virtex-6 FPGA Configuration
High-Performance FPGA Bitstream Transfer up to
800 Mb/s (50 MHz × 16-bits), Ideal for
PCI Express® Endpoint Applications
MultiBoot Bitstream, Design Revision Storage
FPGA Configuration Synchronization (READY_WAIT)
Handshake Signal
ISE® Software Support for In-System Programming via
Xilinx® JTAG Cables
Standard NOR-Flash Interface for Access to Code or
Data Storage
Operation over Full Industrial Temperature Range
(–40°C to +85°C)
Common Flash Interface (CFI)
Low-Power Advanced CMOS NOR-Flash Process
Endurance of 10,000 Program/Erase Cycles Per Block
Power Supplies
Industry-Standard Core Power Supply Voltage
(V
DD
) = 1.8V
3.3V or 2.5V I/O (V
DDQ
) Power Supply Voltage
Memory Organization
128-Mb Main Array Capacity
16-bit Data Bus
Multiple 8-Mb Bank Architecture for Dual
Erase/Program and Read Operation
127 Regular 1-Mb Main Blocks
4 Small 256-Kb Parameter Blocks
Synchronous/Asynchronous Read Modes
Power-On in Synchronous Burst Read Mode
Asynchronous Random Access Mode
Accelerated Asynchronous Page Read Mode
Protection
Default Block Protection at Power-Up
Hardware Write Protection (when V
PP
= V
SS
)
Security
Unique Device Number (64-bits)
One-Time-Programmable (OTP) Registers
Small-Footprint (10 mm × 13 mm) FT64 Packaging
Description
A reliable compact high-performance configuration
bitstream storage and delivery solution is essential for the
high-density FPGAs. Platform Flash XL is the industry's
highest performing configuration and storage device and is
specially optimized for high-performance FPGA
configuration. Platform Flash XL integrates 128 Mb of
in-system programmable flash storage and performance
features for configuration within a small-footprint FT64
package (Figure 5). Power-on burst read mode and
dedicated I/O power supply enable Platform Flash XL to
mate seamlessly with the native SelectMAP configuration
interface. A wide, 16-bit data bus delivers the FPGA
configuration bitstream at speeds up to 800 Mb/s without
wait states. See UG438
, Platform Flash XL Configuration
and Storage Device User Guide, for system-level usage and
performance considerations.
Platform Flash XL is supported for use with Virtex-5 or Virtex-6
FPGAs only. Use with older Virtex families, Spartan® families,
or AES encrypted bitstreams is not supported.
Platform Flash XL is a non-volatile flash storage solution,
optimized for FPGA configuration. The device provides a
READY_WAIT signal that synchronizes the start of the FPGA
configuration process, improving both system reliability and
simplifying board design. Platform Flash XL can download an
XC5VLX330 bitstream (79,704,832 bits) in less than 100 ms,
making the configuration performance of Platform Flash XL
ideal for PCI Express endpoints and other high-performance
applications.
Platform Flash XL is a single-chip configuration solution with
additional system-level capabilities. A standard NOR flash
interface (Figure 2) and support for common flash interface
(CFI) queries provide industry-standard access to the device
memory space. The Platform Flash XL's 128 Mb capacity can
typically hold one or more FPGA bitstreams. Any memory
space not used for bitstream storage can be used to hold
general purpose data or embedded processor code.
8
8
Platform Flash XL High-Density Configuration
and Storage Device
DS617 (v3.0.1) January 07, 2010 Product Specification
R
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