DS586 June 22, 2011 www.xilinx.com 1
Product Specification
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United States and other countries. The PowerPC name and logo are registered trademarks of IBM Corp. and used under license. All other trademarks are the
property of their respective owners.
Introduction
This product specification describes the functionality of
the HWICAP core for the Processor Local Bus (PLB).
The XPS HWICAP (Hardware ICAP) IP enables an
embedded microprocessor, such as the MicroBlaze
™
or
PowerPC
®
processor to read and write the FPGA
configuration memory through the Internal
Configuration Access Port (ICAP) at run time, which
enables a user to write software programs for an
embedded processor that modifies the circuit structure
and functionality during the circuit’s operation.
Features
The XPS HWICAP includes support for resource
reading and modification of the CLB LUTs and
Flip-Flops.
• PLB v4.6 based PLB interface
• Partial bitstream loading is possible
• Supports long frame reads
• Enables Read/Write of CLB LUTs
• Enables Read/Write of CLB Flip-Flop properties
• Support for MicroBlaze and PowerPC embedded
processors
• Support for Virtex-4, Virtex-5, Virtex-6 and
Spartan-6 FPGA families
LogiCORE IP XPS HWICAP
(v5.01a)
DS586 June 22, 2011 Product Specification
LogiCORE IP Facts Table
Core Specifics
Supported
Device Family
(1)
Spartan
®
-6/XA, Virtex
®
-4, Virtex-5, QVirtex-4,
QrVirtex-4, Virtex-6
Supported User
Interfaces
PLB Slave
Resources
See Ta ble 1 5 , Tab l e 16 , Tab le 1 7, and Ta ble 1 8.
Provided with Core
Documentation Product Specification
Design Files VHDL
Example Design Not Provided
Test Bench Not Provided
Constraints File UCF (user constraints file)
Simulation
Model
Not Provided
Tested Design Tools
Design Entry
Tools
Xilinx Platform Studio (XPS)
Simulation Mentor Graphic ModelSim v6.5c and above
Synthesis Tools Xilinx Synthesis Tool (XST)12.4
Support
Provided by Xilinx, Inc.
Notes:
1. For a complete listing of supported devices, see the release
notes for this core.