DS573 April 19, 2010 www.xilinx.com 1
Product Specification
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Introduction
This document describes the specifications for a XPS
Timer/Counter core for the Processor Local Bus.
The XPS Timer/Counter is a 32-bit timer module that
attaches to the PLB bus.
Features
• Connects as a 32-bit slave on PLB V4.6 buses of 32,
64 or 128 bits
• PLB interface with byte-enable support
• Two programmable interval timers with interrupt,
event generation, and event capture capabilities
• Configurable counter width
• One Pulse Width Modulation (PWM) output
• Freeze input for halting counters during software
debug
0
LogiCORE IP XPS
Timer/Counter (v1.02a)
DS573 April 19, 2010
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Product Specification
LogiCORE™ Facts
Core Specifics
Supported Device
Family
Spartan
®
-6, Virtex
®
-6/-6CX,
Spartan-3, Spartan-3A,
Spartan-3E, Automotive
Spartan-3/3E/3A/3A DSP,
Spartan-3 ADSP, Virtex-4,
QVirtex-4, QRVirtex-4,Virtex-5/5FX
Version of Core xps_timer v1.02a
Resources Used
Min Max
Slices
Refer to the Ta bl e 9 , Ta bl e 10 ,
Ta ble 1 1,Ta bl e 12 , and Tabl e 1 3.
LUTs
FFs
Block RAMs N/A
Provided with Core
Documentation Product Specification
Design File Formats VHDL
Constraints File N/A
Verification N/A
Instantiation Template N/A
Reference Designs &
application notes
N/A
Design Tool Requirements
Xilinx Implementation
To o ls
ISE
®
12.1
Verification
MentorGraphics ModelSim 6.5c
and above
Simulation
MentorGraphics ModelSim 6.5c
and above
Synthesis XST
Support
Support provided by Xilinx, Inc.
