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Introduction
This document provides the design specification for the
LogiCORE™ IP XPS_LL_TEMAC Ethernet core. This
core provides a control interface to internal registers via
a 32-bit Processor Local Bus (PLB) Version 4.6 as
described in the IBM CoreConnect 128-Bit Processor Local
Bus, Architectural Specification Version 4.6. This PLB
slave interface supports single beat read and write data
transfers (no burst transfers).
The transmit and receive data interface is via a Xilinx
LocalLink Bus interface as described in this document.
TEMAC is an acronym for Tri-Mode Ethernet Media
Access Controller and is a reference to the three speed
(10, 100, and 1000 Mb/S) capable Ethernet MAC
function available in this core.
This core is based on the Xilinx hard silicon Ethernet
MAC in the Virtex-6, Virtex-5 FXt, LXt, and SXt and
Virtex-4 FX devices and provides a soft Ethernet MAC
option for those and other supported devices.
This core has been designed incorporating the
applicable features described in IEEE Std. 802.3-2002.
Features
• Independent 2K, 4K, 8K, 16K, or 32K Byte TX and
RX data FIFOs for queueing frames
• Filtering of "bad" receive frames
• Support for several PHY interfaces
• Media Independent Interface Management access
to PHY registers
• Full-Duplex operation
• Half-duplex is not supported
• Optional support for jumbo frames up to 9K Bytes
• Optional TX and RX TCP/UDP partial checksum
off load in hardware
• Support for VLAN frames
• Optional TX and RX VLAN tagging, stripping, and
translation
LogiCORE IP XPS LL TEMAC
(v2.03a)
DS537 December 14, 2010 Product Specification
LogiCORE Facts
Core Specifics
Supported Device
Family
Spartan
®
-3A/3A DSP, Spartan-3,
Spartan-3E, Automotive
Spartan 3/3E/3A/3A DSP,
Spartan-6, Virtex
®
-4 /4Q/4QV,
Virtex-5/5FX, Virtex-6/6CX
Version of core xps_ll_temac v2.03a
Resources Used See Ta bl e 1 38 , Table 139,
Ta ble 14 0 , Table 141, and
Ta ble 14 2
.
Special Features None
Provided with Core
Documentation Product Specification
Design File Formats VHDL
Constraints File UCF
Verification VHDL Test bench
Instantiation Template VHDL Wrapper
Reference Designs
and application notes
None
Additional Items None
Design Tool Requirements
Xilinx Implementation
To o ls
ISE
®
11.4 or later
Verification Mentor Graphics ModelSim PE/SE
6.4b or later
Simulation Mentor Graphics ModelSim PE/SE
6.4b or later
Synthesis XST
Support
Provided by Xilinx, Inc.
