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Digital Clock Manager
(DCM) Module
DS485 April 24, 2009
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Product Specification
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Introduction
The Digital Clock Manager (DCM) primitive in Xilinx
FPGA parts is used to implement delay locked loop,
digital frequency synthesizer, digital phase shifter, or a
digital spread spectrum. The digital clock manager
module is a wrapper around the DCM primitive which
allows it to be used in the EDK tool suite.
For more information regarding DCM features, see the
Users Guide of the various FPGA device families at
http://support.xilinx.com.
Features
• Wrapper around the FPGA architecture DCM
primitive; provides full support for use with the
EDK design tools
• Supports both active high and active low reset
• Configurable BUFG insertion
LogiCORE™ Facts
Core Specifics
Supported Device
Family
See EDK Supported Device
Families.
Version of Core dcm_module v1.00d
Resources Used
Min Max
Slices N/A N/A
LUTs 0 1
FFs 3 3
Block RAMs 0 0
Provided with Core
Documentation Product Specification
Design File Formats VHDL
Constraints File N/A
Verification N/A
Instantiation Template N/A
Design Tool Requirements
Xilinx Implementation
Tools
See Too ls for requirements.
Verification
Simulation
Synthesis
Support
Provided by Xilinx, Inc.
