DS482 December 2, 2009 www.xilinx.com 1
Product Specification
© 2003-2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. All other trademarks are the property of their respective owners.
Introduction
The Utility Reduced Logic core applies a logic reduc-
tion function over an input vector to generate a single
bit result. The core is intended as glue logic between
peripherals.
Features
• Configurable size of the input vector
• Configurable reduced logic operation over the
input vector
Utility Reduced Logic (v1.00a)
DS482 December 2, 2009 Product Specification
LogiCORE™ IP Facts
Core Specifics
Supported Device
Family
Spartan
®
-3A/3A DSP, Spartan-3,
Spartan-3E, Automotive
Spartan 3/3E/3A/3A DSP, Spartan-6,
Virtex
®
-4 /4Q/4QV, Virtex-5/5FX,
Virtex-6/6CX
Resources Used
Min Max
Slices 1 6
(1)
LUTs 1 11
(1)
FFs 0 0
Block RAMs 0 0
Provided with Core
Documentation Product Specification
Design File Formats VHDL
Design Tool Requirements
Xilinx Implementation
Tools
ISE
®
11.4 or later
Verification ModelSim PE/SE 6.4b or later
Simulation ModelSim PE/SE 6.4b or later
Synthesis XST
Support
Provided by Xilinx, Inc.
1. For C_SIZE=32. The count increases with C_SIZE.
