0
Data Side OCM Bus v1.0
DS480 April 24, 2009
0 0
Product Specification
DS480 April 24, 2009 www.xilinx.com 1
Product Specification
© 2004-2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. All other trademarks are the property of their respective owners.
Introduction
The DSOCM_V10 core is a data-side On-Chip Memory
(OCM) bus interconnect core. The core connects the
PowerPC
®
405 processor data-side OCM interface to
OCM peripherals, such as the data-side OCM BRAM
controller (DSBRAM IF CNTRL). For information
about the PowerPC 405 processor OCM controller
interface, see the PowerPC 405 Processor Block Reference
Guide.
Features
• Single master - no bus arbitration logic
• Configurable multiple slave capability - contains
read-data multiplexing when used with 2 or more
slaves
LogiCore Facts
Core Specifics
dsocm_v10 v2.00b
Resources Used
Min Max
Slices 0 N/A
0 64
1
0 0
0 0
Provided with Core
Product Specification
VHDL
N/A
N/A
N/A
N/A
Design Tool Requirements
See Tools for requirements.
Support
Provided by Xilinx, Inc.
Supported Device
Family
See EDK Supported Device
Families.
Version of Core
LUTs
FFs
Block RAMs
Documentation
Design File Formats
Constraints File
Verification
Instantiation Template
Reference Designs
Xilinx Implementation
Tools
Verification
Simulation
Synthesis
1. Example for 3 slaves. Size increases with number of slaves