DS471 April 24, 2009 www.xilinx.com 1
Product Specification
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Introduction
The Channel FIFO (CFIFO) contains separate write
(transmit) and read (receive) FIFO designs called
WFIFO and RFIFO, respectively. WFIFO and RFIFO can
be used together or separately, and both are built from
common functional elements such as special low level
counter circuitry and compare functions. A CFIFO is
intended to reside within other cores which require a
multichannel FIFO capability, such as an HDLC
transmitter/receiver. CFIFO does not contain a host bus
interface, instead relying on core instantiation to
provide the interface. FIFOs utilize Virtex®-4 FPGA
block RAM elements as data storage medium. A CFIFO
design incorporates special purpose counters, state
machines, and logic necessary to implement functional
requirements of a channelized FIFO.
Features
• Two independent channel FIFO components
provided: Read CFIFO (for host bus receive data
buffering) and Write CFIFO (for host bus transmit
data buffering).
• User-controlled features include parameters for:
- Setting the number of channels.
- Setting FIFO data depth.
- Setting FIFO data width.
- Setting independent fixed length burst sizes for
each side of a CFIFO. Setting size to zero removes
burst transfer support logic from side and
disables bursts for side of CFIFO.
- Selecting target FPGA family type.
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Channel FIFO (CFIFO)
(v1.00a)
DS471 April 24, 2009
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Product Specification
LogiCORE™ IP Facts
Core Specifics
Supported Device
Family
Spartan®-3, Spartan-3A,
Spartan-3E, Spartan-3A DSP
Virtex®-4
Version of core channel_fifo v1.00a
Resources Used
Min Max
I/O
LUTs 199 345
FFs 61 96
Block RAMs 18 36
Provided with Core
Documentation Product Specification
Design File Formats VHDL
Constraints File UCF
Verification VHDL test bench
Instantiation Template VHDL Wrapper
Design Tool Requirements
Xilinx®
Implementation Tools
ISE® v11
Verification
Mentor Graphics ModelSim v6.4b
and above
Simulation
Mentor Graphics ModelSim v6.4b
and above
Synthesis XST
Support
Support provided by Xilinx, Inc.
