DS440 February 25, 2010 www.xilinx.com 1
Product Specification
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Introduction
This specification is for a DMA Scatter Gather
controller which can scale up to a relatively large
number of channels (hundreds). Many concepts from
an earlier Xilinx DMA Scatter Gather controller (see
Reference [1]) are retained and some are dropped or
altered to cater to the needs of a channelized
implementation and the use of block RAM to store
channel state.
An example of a communications controller that needs
a high number of DMASG channels is an HDLC
controller with multiple physical channels and multiple
TDM (time-division multiplexed) subchannels per
physical channel. The present DMASG controller is
specified with such a system, or similar one, in mind.
The Channelized Direct Memory Access and Scatter
Gather controller is packaged as a service within a
Xilinx IPIF bus-connection block.
Features
• Available as a service in selected IPIFs
• Supports up to 16 physical channels
• Supports up to 64 subchannels per physical channel
• Block RAM implementation limits resource usage as
number of channels scales up
• Supports packet SG, simple SG and simple DMA
• Status FIFO interface for synchronization with
communications controller
• Event FIFO for reporting interrupts
• Supports optional Interrupt coalescing
0
Channelized Direct Memory
Access and Scatter Gather
(v1.00a)
DS440 February 25, 2010
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Product Specification
LogiCORE™ IP Facts
Core Specifics
Supported Device
Family
Spartan®-3, Spartan-3E,
Virtex®-4
Version of core chan_dma_sg v1.00a
Resources Used
Min Max
I/O N/A N/A
LUTs 830 960
FFs 330 370
Block RAMs 1 8
Provided with Core
Documentation Product Specification
Design File Formats VHDL
Constraints File None
Verification N/A
Instantiation Template VHDL Wrapper
Design Tool Requirements
Xilinx Implementation
Tools
ISE® v11.1
Verification
Mentor Graphics ModelSim v6.4b
and above
Simulation
Mentor Graphics ModelSim v6.4b
and above
Synthesis XST
Support
Support provided by Xilinx, Inc.
