DS429 April 24, 2009 www.xilinx.com 1
Product Specification
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Introduction
A DCR (Device Control Register Bus v29) Interrupt
Controller (INTC) core is composed of a bus-centric
wrapper containing the INTC core and a DCR interface.
The INTC core is a simple, parameterized interrupt
controller that, along with the appropriate bus
interface, attaches to the DCR Bus.
In this document INTC and DCR INTC are used
interchangeably to refer to functionality or interface
signals that are common to all variations of the
Interrupt Controller. When the discussion switches to a
bus centric version, then the interrupt controller will be
referred to as DCR INTC.
Features
• DCR v2.0 bus interface (IBM SA-14-2525-00 32-bit
DCR Bus Architecture Specifications, v2.9)
• Supports address bus width of 10-bits and data bus
width of 32-bits for DCR interface
• Configurable number of (up to 32) interrupt inputs
• Single interrupt output
• Can be easily cascaded to provide additional
interrupt inputs
• Priority between interrupt requests is determined
by vector position. The least significant bit (LSB, in
this case bit 0) has the highest priority
• Interrupt Enable Register for selectively disabling
individual interrupt inputs
• Master Enable Register for disabling interrupt
request output
DCR Interrupt Controller (v2.00a)
DS429 April 24, 2009 Product Specification
LogiCORE™ Facts
Core Specifics
Supported Device
Family
See EDK Supported Device Families
.
Version of Core dcr_intc v2.00a
Resources Used
Min Max
Slices
See Tabl e 13 and Ta ble 14 .FFs
LUTs
Block RAMs N/A
Provided with Core
Documentation Product Specification.
Design File Formats VHDL
Constraints File N/A
Verification N/A
Instantiation Template N/A
Reference Designs None
Design Tool Requirements
Xilinx Implementation
Too l s
See Too ls
for requirements.
Verification
Simulation
Synthesis
Support
Provided by Xilinx, Inc.
