DS403 December 13, 2007 www.xilinx.com 1
Product Specification
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Introduction
The Processor Local Bus Version 4.6 (PLBV46) to
On-chip Peripheral Bus (OPBv20) Bridge translates
PLBv46 transactions into OPB transactions. The system
designer uses the bridge in systems where a PLBv46
master device requires access to legacy OPB
peripherals.
Features
• Bridges transactions as a 32-bit PLBv46 slave and
32-bit OPBv20 master.
• PLBv46 Slave interface
- Supports connections to a 32-, 64-, or 128-bit
PLBv46 bus and transactions from 32-, 64- and
128-bit masters that can talk to 32-bit slaves.
- Decodes up to four separate address ranges with
programmable lower and upper address
boundaries for each range
- Single transfers of 1-4 bytes. Read data mirroring
supports conversion cycles from larger masters.
- Supports only fixed length, burst transactions of
up to sixteen quad-words, double-words, words,
(for appropriately sized masters.)
- Cacheline transactions of 4 and 8 words
- Supports up to 8 PLBv46 masters (number of
PLBv46 masters configurable via a design
parameter)
- Supports low latency point-to-point topology
- 16-word buffer to increase PLBv46 bus utilization
via posted writes.
• OPB Master interface
- Utilizes byte enable interface
- The OPB master re-attempts all slave retried
transactions until they complete
0
PLBV46 to OPB Bridge
(v1.00a)
DS403 December 13, 2007
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Product Specification
LogiCORE™ Facts
Core Specifics
Supported Device
Family
Spartan
™
3, Virtex™-II Pro,
Virtex-4, Virtex-5,
Version of Core
plbv46_opb_
bridge
v1_00_a
Resources Used
Min Max
Slices 180 199
LUTs 285 312
FFs 188 244
Block RAMs 0 0
Provided with Core
Documentation Product Specification
Design File Formats VHDL
Constraints File N/A
Verification N/A
Instantiation Template N/A
Reference Designs None
Design Tool Requirements
Xilinx Implementation
Tools
9.1i or later
Verification N/A
Simulation ModelSim SE/EE 6.1e or later
Synthesis XST
Support
Support provided by Xilinx, Inc.
