DS205 October 16, 2012 www.xilinx.com 1
Product Specification v3.167 & v4.18
© Copy right 201 0–2012 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex , Vivado, Zynq, and other designated brands included herein are
trademarks of Xilinx in the United States and other countries. PCI, PCI Express, PCIe, and PCI-X are trademarks of PCI-SIG. All other trademarks are the property
of their respective owners.
Features
• Fully compatible 64-bit, 66/33 MHz LogiCORE™
IP Initiator/Target core for PCI™
• Customizable, programmable, single-chip solution
• Pre-defined implementation for predictable timing
• Incorporates Xilinx Smart-IP technology
• 3.3V operation at 0–66 MHz
• 5.0V operation at 0–33 MHz
• Fully verified design tested with Xilinx proprietary
test bench and hardware
• Delivered through Xilinx
®
CORE Generator™ tool
and Vivado™ IP Catalog
• CardBus compliant
• Supported initiator functions:
• Configuration read, configuration write
• Memory read, memory write, MRM, MRL
• Interrupt acknowledge, special cycles
• I/O read, I/O write
• Supported target functions:
• Type 0 configuration space header
• Up to three base address registers (MEM or
I/O with adjustable block size from 16 bytes to
2 GB)
• Medium decode speed
• Parity generation, parity error detection
• Configuration read, configuration write
• Memory read, memory write, MRM, MRL
• Interrupt acknowledge
• I/O read, I/O write
• Target abort, target retry, target disconnect
LogiCORE IP 64-Bit
Initiator/Target v3 & v4 for PCI
DS205 October 16, 2012 Product Specification v3.1 67 & v4.18
LogiCORE IP Facts
Core Specifics
Supported Device
Family
(1)
1. For a complete listing of supported devices, see the release notes
for this core.
See Table 1.
Resource
Utilization
(2)
2. Resource utilization depends on core configuration and design
requirements. Unused resources are trimmed by the Xilinx
technology mapper. Utilization figures reported represent a
maximum configuration.
v4 Core v3 Core
LUTs 565 724
Slice Flip-Flops 404 732
IOB Flip-Flops 94 176
IOBs 94 89
GCLK
(3)
3. Designs running at 66 MHz in Virtex
®
-4 and Virtex-5 FPGA imple-
mentations require additi onal BUFG for 200 MHz reference clock.
2 1
Provided with Core
Documentation
Product Specification v3 & v4
Getting Started Guide v3
User Guide v4
User Guide v3
Design File Formats
ISE: VHDL/Verilog Simulation Model
ISE: NGC Netlist (v4 core only)
ISE: NGO Netlist (v3 core only)
Vivado: Encrypted RTL
Constraints File
ISE: UCF
Vivado: XDC
Test Bench VHDL/Verilog Example Test Bench
Instantiation Template VHDL/Ver ilog Wrapper
Example Designs VHDL/Verilog Example Design
Tested Design Flows
(4)
4. For the supported versions of the tools, see the Xilinx Design
Tools: Release Notes Guide.
Design Entry
ISE
®
Design Suit e v 14 . 3
Vivado Design Suite v2012.3
(5)
5. Supports 7 series devices only.
Simulation
Mentor Graphics Mode lSim
Cadence Incisive Enterprise
Simulator (IES)
Synthesis
Xilinx XST
Viv ado Synthesis
Support
Provided by Xilinx @ www.xilinx.com/support
