DS176 October 5, 2016 www.xilinx.com
Advance Product Specification 1
Introduction
The Xilinx
®
Zynq
®
-7000 All Programmable SoC and
7 series FPGAs memory interface solutions cores provide
high-performance connections to DDR3 and DDR2
SDRAMs, QDR II+ SRAM, RLDRAM II/RLDRAM 3, and
LPDDR2 SDRAM.
DDR3 and DDR2 SDRAMs
This section discusses the features, applications, and
functional description of Xilinx 7 series FPGAs memory
interface solutions in DDR3 and DDR2 SDRAMs. These
solutions are available with an optional AXI4 slave
interface.
DDR3 SDRAM Features
• Component support for interface widths up to 72 bits
• Single and dual rank UDIMM, RDIMM, and SODIMM
support
• DDR3 (1.5V) and DDR3L (1.35V)
• 1, 2, 4, and 8 Gb density device support
• 8-bank support
• x8 and x16 device support
• 8:1 DQ:DQS ratio support
• Configurable data bus widths (multiples of 8, up to
72 bits)
• 8-word burst support
• Support for 5 to 14 cycles of column-address strobe
(CAS) latency (CL)
• On-die termination (ODT) support
• Support for 5 to 10 cycles of CAS write latency
• ZQ calibration – initial and periodic (configurable)
• Write leveling support for DDR3 (fly-by routing
topology required for DDR3 component designs)
• JEDEC
®
-compliant DDR3 initialization support
• Source code delivery in Verilog and VHDL (top-level
files only)
• 4:1 and 2:1 memory to FPGA logic interface clock ratio
• ECC support
• I/O Power Reduction option reduces average I/O
power by automatically disabling DQ/DQS IBUFs and
internal terminations during writes and periods of
inactivity
• Internal V
REF
support
• Multicontroller support for up to eight controllers
• Two controller request processing modes:
o Normal: reorder requests to optimize system
throughput and latency
o Strict: memory requests are processed in the order
received
Zynq-7000 AP SoC and 7 Series Devices
Memory Interface Solutions (v4.1)
DS176 October 5, 2016 Advance Product Specification
LogiCORE™ IP Facts Table
Core Specifics
Supported
Device Family
(1)
Zynq
®
-7000 All Programmable SoC,
Virtex
®
-7
(2)
, Kintex
®
-7
(2)
, Artix
®
-7
Supported
Memory
DDR3 Component and DIMM, DDR2
Component and DIMM, QDR II+, RLDRAM II,
RLDRAM 3, and LPDDR2 SDRAM Components
Resources See Table 1.
Provided with Core
Documentation Product Specification
User Guide
Design Files Verilog, VHDL (top-level files only)
Example Design Verilog, VHDL (top-level files only)
Test Bench Not Provided
Constraints File XDC
Supported
S/W Driver
N/A
Tested Design Flows
(3)
Design Entry
Vivado
®
Design Suite
Simulation For supported simulators, see t he
Xilinx Design Tools: Rele ase Notes G uide
.
Synthesis
(4)
Vivado Synthesis
Support
Provided by Xilinx at the Xilinx Support web page.
Notes:
1. For a complete listing of supported devices, see the release notes for
MIG.
2. See the Virtex-7 FPGAs Data Sheet: DC and Switching Characteristics
or the Kintex-7 FPGAs Data Sheet: DC and Switching Characteristics for
performance information.
3. For the supported versions of the tools, see the
Xilinx Design Tools: Release Notes Guide
.
4. The standard synthesis flow for Synplify is not supported for the
core.
