DS174 (v2.0) March 22, 2010 www.xilinx.com
Product Specification 1
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other countries. PCI, PCI Express, PCIe, and PCI-X are trademarks of PCI-SIG. PowerPC is a trademark of IBM Corp. and is used under license. All other trademarks are the
property of their respective owners.
General Description
The Defense-grade Virtex®-5Q family provides the newest, most capable features in the aerospace and defense industry from the
reprogrammable FPGA market leader. The Virtex-5Q family delivers on Size, Weight, and Power - Cost (SWAP-C) reduction requirements
while increasing performance and density for higher integration. Based on the proven commercial Virtex-5 FPGAs, the Virtex-5Q family
offers greater operational temperature ranges off the shelf to fit the needs of the aerospace and defense customer base as well as
ruggedized packaging for protection against tin-whiskering and harsh manufacturing processes. Mask-set control and long-term product
availability are also standard. Using the second generation Advanced Silicon Modular Block (ASMBL™) column-based architecture, the
Virtex-5Q family contains four distinct sub-families, the most offered by any FPGA vendor. Each sub-family contains a different ratio of
features to address the needs of a wide variety of advanced designs. In addition to the most advanced, high-performance logic fabric,
Virtex-5Q FPGAs contain many dedicated system-level blocks, including powerful 36 Kbit block RAM/FIFOs, second generation 25 x 18
DSP slices, SelectIO™ technology with built-in digitally-controlled impedance, ChipSync™ technology source-synchronous interface
blocks, system monitor functionality, enhanced clock management tiles (CMTs) with integrated digital clock managers (DCM) and phase-
locked-loop (PLL) clock generators, and advanced configuration options. Additional device-dependent features include power-optimized,
high-speed serial transceiver blocks for enhanced serial connectivity, PCI Express® compliant integrated Endpoint blocks, tri-mode
Ethernet Media Access Controllers (Ethernet MACs), and high-performance PowerPC® 440 microprocessor embedded blocks. These
features allow advanced logic designers to build the highest levels of performance and functionality into their FPGA-based systems. The
Virtex-5Q LX, LXT, SXT, and FXT FPGAs also include advanced high-speed serial connectivity and link/transaction layer capability.
Virtex-5Q FPGAs offer the best solution for addressing the needs of aerospace and defense logic, DSP, and embedded systems
designers for a host of applications including imaging, secure applications, electronic warfare, packet processing, and more.
Summary of Virtex-5Q FPGA Features
• Four sub-families: LX, LXT, SXT, and FXT
• Virtex-5Q LX: High-performance general logic applications
• Virtex-5Q LXT: High-performance logic with advanced serial
connectivity
• Virtex-5Q SXT: High-performance signal processing
applications with advanced serial connectivity
• Virtex-5Q FXT: High-performance embedded systems with
advanced serial connectivity
• Cross-family compatibility
• LXT, SXT, and FXT devices are footprint compatible in the
same package using adjustable voltage regulators
• All devices are pin-to-pin compatible with commercial
Virtex-5 devices with the same package within sub-families
for prototyping.
• Most advanced, high-performance, optimal-utilization,
FPGA logic
• Real 6-input look-up table (LUT) technology
• Dual 5-LUT option
• Improved reduced-hop routing
• 64-bit distributed RAM option
• SRL32/Dual SRL16 option
• Powerful CMT clocking
• DCM blocks for zero delay buffering, frequency synthesis,
and clock phase shifting
• PLL blocks for input jitter filtering, zero delay buffering,
frequency synthesis, and phase-matched clock division
• 36 Kbit block RAM/FIFOs
• True dual-port RAM blocks
• Enhanced optional programmable FIFO logic
• Programmable
- True dual-port widths up to x36
- Simple dual-port widths up to x72
• Built-in optional error-correction circuitry
• Optionally program each block as two independent 18 Kbit
blocks
• High-performance parallel SelectIO technology
• 1.2 to 3.3V I/O Operation
• Source-synchronous interfacing using ChipSync technology
• Digitally-controlled impedance (DCI) active termination
• Flexible fine-grained I/O banking
• High-speed memory interface support
• Advanced DSP48E slices
• 25 x 18, two’s complement, multiplication
• Optional adder, subtracter, and accumulator
• Optional pipelining
• Optional bitwise logical functionality
• Dedicated cascade connections
• Flexible configuration options
• SPI and Parallel Flash interface
• Multi-bitstream support with dedicated fallback
reconfiguration logic
• Auto bus width detection capability
• System Monitoring capability on all devices
• On-chip/Off-chip thermal monitoring
• On-chip/Off-chip power supply monitoring
• JTAG access to all monitored quantities
• Integrated Endpoint blocks for PCI Express designs
• LXT, SXT, and FXT FPGAs
• Compliant with the PCI Express Base Specification 1.1
• x1, x4, or x8 lane support per block
• Works in conjunction with RocketIO™ transceivers
• Tri-mode 10/100/1000 Mb/s Ethernet MACs
• LXT, SXT, and FXT FPGAs
• RocketIO transceivers can be used as PHY or connect to
external PHY using many soft Media Independent Interface
(MII) options
• RocketIO GTP transceivers 100 Mb/s to 3.75 Gb/s
• LXT and SXT FPGAs
• RocketIO GTX transceivers 150 Mb/s to 6.5 Gb/s
•FXT FPGAs only
• PowerPC 440 microprocessors
•FXT FPGAs only
• RISC architecture
• 7-stage pipeline
• 32 Kbyte instruction and data caches included
• Optimized processor interface structure (crossbar)
• 65 nm copper CMOS process technology
• 1.0V core voltage
• Rugged EF packaging
• Epoxy coated internal chip caps for superior solvent clean
resistance (all except FF323 and FF1738 pin packages)
• Fully tin/lead packaging including chip-cap finish
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Virtex-5Q Family Overview
DS174 (v2.0) March 22, 2010
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Product Specification