DS138 April 19, 2010 www.xilinx.com 1
Product Specification
© 2007-2008, 2010. Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE and other designated brands included herein are trademarks of Xilinx in the United States
and other countries. PCI, PCI-SIG, PCI EXPRESS, PCIE, PCI-X, PCI HOT PLUG, MINI PCI, EXPRESSMODULE, and the PCI, PCI-X, PCI HOT PLUG, and
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Introduction
The LogiCORE™ IP Virtex
®
-4 FX FPGA RocketIO™
Multi-Gigabit Transceiver (MGT) Wizard automates
the task of creating HDL wrappers to configure the
high-speed serial multi-gigabit transceivers in the
Virtex-4 FX family. The menu-driven interface allows
one or more transceivers to be configured using pre-
defined templates for popular industry standards, or
from scratch, to support a wide variety of custom pro-
tocols.
The Wizard produces a wrapper, an example design,
and a test bench for rapid integration and verification
of the serial interface with your custom function.
Features
• Creates customized HDL wrappers to configure
Virtex-4 FX FPGA RocketIO MGTs
• Users can configure Virtex-4 FX FPGA MGTs to
conform to industry standard protocols using
predefined templates, or tailor the templates for
custom protocols
• Templates include support for the following
specifications: Aurora 8B/10B, Fibre Channel,
Gigabit Ethernet, GPON, Infiniband, OC12, PCI
Express®, SATA 1.5 Gbps and SATA 3 Gbps, Serial
RapidIO, and XAUI
• Automatically configures analog settings
• Each custom wrapper includes example design, test
bench; and both implementation and simulation
scripts
Note:
See the Virtex-4 FX FPGA RocketIO Multi-Gigabit
Transceiver Wizard Getting Started Guide [Ref 2] for a
general overview of the wrapper creation procedure.
LogiCORE IP Virtex-4 FX FPGA
RocketIO Multi-Gigabit
Transciever Wizard v1.7
DS138 April 19, 2010 Product Specification
LogiCORE IP Facts
Core Specifics
Supported Device
Family
(1)
Virtex-4 FX
Provided with Core
Documentation Product Specification
Getting Started Guide
Design File Formats Verilog and VHDL
Constraints File .ucf (user constraints file)
Verification Example Design and Test Bench
Instantiation Template Verilog or VHDL Wrapper
Design Tool Requirements
Xilinx Implementation
To o ls
ISE
®
12.1
(2)
Verification Mentor Graphics ModelSim 6.5c
and above
Simulation Mentor Graphics ModelSim 6.5c
and above
Synthesis
XST 12.1
Synopsys Synplify Pro D-2009.12
Support
Provided by Xilinx, Inc. at http://www.xilinx.com/support
1. For more information on the Virtex-4 devices, see
Virtex-4 Family Overview [Ref 1]
2. ISE Service Packs can be downloaded from
http://www.xilinx.com/support/download.htm
