DS108-1 (v1.7) April 3, 2007 www.xilinx.com 1
Product Specification
© 2002-2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
k
Features
• AEC-Q100 device qualification and full PPAP support
available in both extended temperature Q-grade and
I-grade.
• Guaranteed to meet full electrical specifications over
T
A
= -40° C to +105° C with T
J
Maximum = +125° C
(Q-grade)
• System frequency up to 64.5 MHz (15.5 ns)
• Available in small footprint packages
• Optimized for high-performance 3.3V systems
- 5V tolerant I/O pins accept 5V, 3.3V, and 2.5V
signals — ideal for multi-voltage system interfacing
and level shifting
- Technology: 0.35 μm CMOS process
• Advanced system features
- In-system programmable enabling higher system
reliability through reduced handling and reducing
production programming times
- Superior pin-locking and routability with
FastCONNECT™ II switch matrix allowing for
multiple design iterations without board re-spins
- Input hysteresis on all user and boundary-scan pin
inputs to reduce noise on input signals
- Bus-hold circuitry on all user pin inputs which
reduces cost associated with pull-up resistors and
reduces bus loading
- Full IEEE Standard 1149.1 boundary-scan (JTAG)
for in-system device testing
· Fast concurrent programming
• Slew rate control on individual outputs for reducing EMI
generation
• Refer to XC9500XL Family data sheet (DS054) for
architecture description
• Refer to XA9536XL data sheet (DS598), the
XA9572XL data sheet (DS599), and the XA95144XL
data sheet (DS600) for pin tables
• Xilinx received ISO/TS 16949 Certification in March
2005.
WARNING: Programming temperature range of
T
A
= 0° C to +70° C
Description
The XA9500XL 3.3V CPLD Automotive XA product family is
targeted for leading-edge, high-performance automotive
applications that require either automotive industrial (–40°C
to +85°C ambient) or extended (–40°C to +105°C ambient)
temperature reconfigurable devices.
Power Estimation
Power dissipation in CPLDs can vary substantially depend-
ing on the system frequency, design application and output
loading. Each macrocell in an XA9500XL automotive device
must be configured for low-power mode (default mode for
XA9500XL devices). In addition, unused product-terms and
macrocells are automatically deactivated by the software to
further conserve power.
For a general estimate of I
CC
, the following equation may be
used:
I
CC
(mA) = MC(0.052*PT + 0.272) + 0.04 * MC
TOG
*MC* f
where:
MC = # macrocells
PT = average number of product terms per macrocell
f = maximum clock frequency
MC
TOG
= average % of flip-flops toggling per clock
(~12%)
This calculation is based on typical operating conditions
using a pattern of 16-bit up/down counters in each Function
Block with no output loading. The actual I
CC
value varies
with the design application and should be verified during
0
XA9500XL Automotive CPLD
Product Family
DS108-1 (v1.7) April 3, 2007
00
Product Specification
R
Table 1: XA9500XL Device Family
Device Temperature Grade Macrocells Usable Gates Registers f
SYSTEM
(MHz)
XA9536XL I, Q 36 800 36 64.5
XA9572XL I, Q 72 1,600 72 64.5
XA95144XL I 144 3,200 144 64.5
